LP3907-Q1 Datasheet, PDF (17/53 Pages) Texas Instruments – Dual High-Current Step-Down DC-DC And Dual Linear Regulator

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LP3907-Q1
SNVSA55A – DECEMBER 2014 – REVISED MAY 2015
Feature Description (continued)
8.3.2.2 Circuit Operation Description
A buck converter contains a control block, a switching PFET connected between input and output, a synchronous
rectifying NFET connected between the output and ground (BCKGND pin) and a feedback path. During the first
portion of each switching cycle, the control block turns on the internal PFET switch. This allows current to flow
from the input through the inductor to the output filter capacitor and load. The inductor limits the current to a
ramp with a slope of
V_IN - V_OUT
L
(1)
by storing energy in a magnetic field. During the second portion of each cycle, the control block turns the PFET
switch off, blocking current flow from the input, and then turns the NFET synchronous rectifier on. The inductor
draws current from ground through the NFET to the output filter capacitor and load, which ramps the inductor
current down with a slope of
-V_OUT
L
(2)
The output filter stores charge when the inductor current is high, and releases it when low, smoothing the voltage
across the load.
8.3.2.3 PWM Operation
During PWM operation the converter operates as a voltage-mode controller with input voltage feed forward. This
allows the converter to achieve excellent load and line regulation. The DC gain of the power stage is proportional
to the input voltage. To eliminate this dependence, feed forward voltage inversely proportional to the input
voltage is introduced.
8.3.2.4 Internal Synchronous Rectification
While in PWM mode, the buck uses an internal NFET as a synchronous rectifier to reduce rectifier forward
voltage drop and associated power loss. Synchronous rectification provides a significant improvement in
efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier
diode.
8.3.2.5 Current Limiting
A current limit feature allows the converter to protect itself and external components during overload conditions.
PWM mode implements current limiting using an internal comparator that trips at 1.5 A for Buck1 and at 1 A for
Buck2 (typ). If the output is shorted to ground the device enters a timed current limit mode where the NFET is
turned on for a longer duration until the inductor current falls below a low threshold, ensuring inductor current has
more time to decay, thereby preventing runaway.
8.3.2.6 PFM Operation
At very light loads, the converter enters PFM mode and operates with reduced switching frequency and supply
current to maintain high efficiency.
The part automatically transitions into PFM mode when either of two conditions occurs for a duration of 32 or
more clock cycles:
1. The inductor current becomes discontinuous, or
2. The peak PMOS switch current drops below the I_MODE level
(Typically
I_MODE
<
66
mA
+
V_IN
160:
)
(3)
During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage
during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy
load. The PFM comparators sense the output voltage via the feedback pin and control the switching of the output
FETs such that the output voltage ramps between 0.8% and 1.6% (typical) above the nominal PWM output
voltage. If the output voltage is below the ‘low’ PFM comparator threshold, the PMOS power switch is turned on.
It remains on until the output voltage exceeds the ‘high’ PFM threshold or the peak current exceeds the I_PFM level
set for PFM mode. The typical peak current in PFM mode is:
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