LP3907-Q1 Datasheet, PDF (43/53 Pages) Texas Instruments – Dual High-Current Step-Down DC-DC And Dual Linear Regulator

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LP3907-Q1
SNVSA55A – DECEMBER 2014 – REVISED MAY 2015
where
• η is the efficiency for the specific condition taken from efficiency graphs.
(17)
9.2.3 Application Curves
100
90
80
70
60
50
40
30
20
10
0.1
V_OUT = 2 V
V_IN = 2.8V
V_IN = 3.6V
V_IN = 5.5V
1
10
100
OUTPUT CURRENT (mA)
L= 2.2 µH
1000
Figure 47. Efficiency vs Output Current
(Forced PWM Mode)
100
90
V_IN= 4.5V
80
V_IN= 5.5V
70
60
50
40
0.1
V_OUT = 2 V
1
10
100
OUTPUT CURRENT (mA)
L= 2.2 µH
1000
Figure 48. Efficiency vs Output Current
(PWM-to-PFM Mode)
10 Power Supply Recommendations
If the EN_T is used to power up the device instead individual ENs , then VIN must be stable for approximately 8
ms minimum before EN_T be asserted high to ensure internal bias, reference, and the Flexible POR timing are
stabilized. This initial EN_T delay is necessary only upon first time device power on for power sequencing
function to operate properly.
10.1 Analog Power Signal Routing
All power inputs should be tied to the main VDD source (for example, battery), unless the user wishes to power it
from another source. (that is, external LDO output).
The analog VDD inputs power the internal bias and error amplifiers, so they should be tied to the main VDD. The
analog VDD inputs must have an input voltage between 2.8 V and 5.5 V, as specified in the Recommended
Operating Conditions (Bucks) table earlier in the datasheet.
The other VINs (VINLDO1, VINLDO2) can have inputs lower than 2.8 V, as long as the input it higher than the
programmed output (0.3 V).
The analog and digital grounds should be tied together outside of the chip to reduce noise coupling.
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