DS90C387R_15 Datasheet, PDF (5/32 Pages) Texas Instruments – Dual 12-Bit Double Pumped Input LDI Transmitter - VGA/UXGA

DS90C387R
www.ti.com
SNLS062G – NOVEMBER 2000 – REVISED JANUARY 2014
Recommended Transmitter Input Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. Device driving the transmitter
inputs should comply to this table of recommendations.
Symbol
Parameter
Min
Typ
Max
Unit
TCIT
TCIP
TCIH
TxCLK IN Transition Time (Figure 6)
TxCLK IN Period (Figure 7)
TxCLK in High Time (Figure 7)
DUAL = Gnd or V_CC
0.8
1.2
2.4
ns
DUAL = Gnd or V_CC
11.76
T
40
ns
0.4T
0.5T
0.6T
ns
TCIL
TxCLK in Low Time (Figure 7)
0.4T
0.5T
0.6T
ns
VDDQ
Low Swing Voltage Amplitude from GMCH
1.0
1.8
V
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.⁽¹⁾
Symbol
Parameter
Min
Typ
Max
Unit
LLHT
LVDS Low-to-High Transition Time (Figure 5), PRE = no connect (minimum
pre-empahsis).
0.14
0.9
ns
LVDS Low-to-High Transition Time (Figure 5), PRE = V_CC (max. pre-
empahsis).
0.11
0.7
ns
LHLT
LVDS High-to-Low Transition Time (Figure 5), PRE = no connect (mini. pre-
empahsis).
0.16
0.9
ns
LVDS High-to-Low Transition Time (Figure 5), PRE = V_CC (max. pre-
empahsis).
0.11
0.7
ns
TCCS
TPPOS0
TxOUT Channel to Channel Skew
Transmitter Output Pulse Position for Bit0 from
TxCLKout rising edge.
f = 85MHz ⁽²⁾
100
ps
-300
0
+300
ps
TPPOS1 Transmitter Output Pulse Position for Bit1 from
TxCLKout rising edge.
1.38
1.68
1.98
ns
TPPOS2 Transmitter Output Pulse Position for Bit2 from
TxCLKout rising edge.
3.06
3.36
3.66
ns
TPPOS3 Transmitter Output Pulse Position for Bit3 from
TxCLKout rising edge.
4.74
5.04
5.34
ns
TPPOS4 Transmitter Output Pulse Position for Bit4 from
TxCLKout rising edge.
6.42
6.72
7.02
ns
TPPOS5 Transmitter Output Pulse Position for Bit5 from
TxCLKout rising edge.
8.10
8.40
8.70
ns
TPPOS6 Transmitter Output Pulse Position for Bit6 from
TxCLKout rising edge.
9.78
10.08
10.38
ns
TSTC
TxIN Setup to TxCLK IN in low swing mode at 85 MHz (Figure 8)
1.8
ns
THTC
TxIN Hold to TxCLK IN in low swing mode at 85 MHz (Figure 8)
2
ns
TJCC
Transmitter Jitter Cycle-to-cycle (Figure 13
Figure 14) ⁽³⁾, DUAL = Gnd, V_CC = 3V
f = 85 MHz
f = 65 MHz
110
150
ps
80
120
ps
f = 32.5 MHz
75
115
ps
TPLLS
Transmitter Phase Lock Loop Set (Figure 9)
10
ms
TPDD
TPDL
Transmitter Powerdown Delay (Figure 10)
Transmitter Input to Output Latency (Figure 11) f = 32.5/65/85 MHz ⁽⁴⁾
100
ns
1.5TCIP
ns
+4.1
(1) Typical values are given for V_CC = 3.3V and T _A = +25°C. Device tested in Non-Balanced mode only.
(2) The parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over PVT(process,
voltage and temperature) range.
(3) The limits are based on bench characterization of the device's jitter response over the power supply voltage range. Output clock jitter is
measured with a cycle-to-cycle jitter of ±2ns applied to the input clock signal while data inputs are switching (see Figure 13 and
Figure 14). A jitter event of 2ns, represents worse case jump in the clock edge from most graphics VGA chips currently available. This
parameter is used when calculating system margin as described in AN-1059.
(4) From V = 1.5V of CLKINP to V_DIFF= 0V of CLK1P when R_FB = High, DUAL = Low or High, BAL = Low.
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