DS90C387R_15 Datasheet, PDF (14/32 Pages) Texas Instruments – Dual 12-Bit Double Pumped Input LDI Transmitter - VGA/UXGA

DS90C387R
SNLS062G – NOVEMBER 2000 – REVISED JANUARY 2014
www.ti.com
Table 5. Register Field Definitions (continued)
Field
FRQ_LOW
FRQ_HIGH
PD
EDGE
BSEL
DSEL
HEN
VEN
MDI
HTPLG ⁽¹⁾
RSEN
TSEL
MSEL [2:0]
VLOW
CTL [3:1]
CFG [7:0]⁽¹⁾
VDJK [7:0]⁽¹⁾
DK [3:1]⁽¹⁾
DKEN ⁽¹⁾
Access
RO
RO
RW
RW
RW
RW
RW
RW
RW
RO
RO
RW
RW
RO
RW
RO
RW
RW
RW
Description
25 MHz is Low frequency limit for the current mode, value is 19h.
85 MHz is High frequency limit for the current mode, value is 55h.
Power down mode, default = 1.
0 - power down only the LVDS drivers. Output of this device will be in TRI-STATE mode. Other
circuitry are still active.
1 - normal operation.
Edge select (same function as R_FB pin), default = 1.
0 - input data is rising edge latched (rising edge latched first in 12-bit and two 12-bit mode).
1 - input data is falling edge latched (falling edge latched first in 12-bit and two 12-bit mode).
Input bus select (same as DUAL pin), default = 0.
0 - one 12-bit bus.
1 - two 12-bit bus.
Dual level clock select (same function as DSEL pin), default = 1.
0 - input clock is differential.
1 - input clock is single-ended (up to 65MHz). CLKINM and V_REF pin are internally connected.
Horizontal sync enable, default = 1.
0 - HSYNC input is transmitted as fixed LOW.
1 - HSYNC input is transmitted as it is.
Vertical sync enable, default = 1.
0 - VSYNC input is transmitted as fixed LOW.
1 - VSYNC input is transmitted as it is.
Monitor Detect Interrupt, default = 1.
0 - Detection signal has changed logical level (write "1" to this bit to clear).
1 - Detection signal has not changed state.
Feature not implemented.
This bit is a ”1 “ if a powered on receiver is connected to the transmitter outputs, ” 0 “ otherwsie.
This function is only available for use in DC-coupled systems. Default=0.
Interrupt generation method, default=0.
0 - Interrupt bit (MDI) is generated by monitoring RSEN.
1 - Interrupt bit (MDI) is generated by monitoring HTPLG.
Select source for the MSEN output pin. Default valus is 001.
000 - Force MSEN output HIGH (disabled).
001 - Output the value of MDI bit (interrupt). This is default.
010 - Output the value of RSEN bit (receiver detect).
011 - Output the value of HTPLG bit (hot plug detect).
1xx - Reserved.
This bit is an 1 if the VREF signal indicates low swing inputs. Default=1.
It is a 0 if VREF indicates high swing inputs.
General purpose inputs.
Feature not implemented.
Reserved.
Feature not implemented.
Feature not implemented.
(1) Features not implemented on DS90C387R
14
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