DS90C387R_15 Datasheet, PDF (10/32 Pages) Texas Instruments – Dual 12-Bit Double Pumped Input LDI Transmitter - VGA/UXGA

DS90C387R
SNLS062G – NOVEMBER 2000 – REVISED JANUARY 2014
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C—Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and
max
Tppos—Transmitter output pulse position (min and max)
RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) + ISI (Inter-symbol interference)
Cable Skew—typically 10 ps–40 ps per foot, media dependent
A. Cycle-to-cycle jitter is less than 150 ps at 85 MHz
B. ISI is dependent on interconnect length; may be zero
Figure 12. Receiver Skew Margin
Figure 13. TJCC Test Setup - DS90C387R
Figure 14. Timing Diagram of the Input Cycle-to-Cycle Clock Jitter
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