DS90C387R_15 Datasheet, PDF (13/32 Pages) Texas Instruments – Dual 12-Bit Double Pumped Input LDI Transmitter - VGA/UXGA

DS90C387R
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Therefore, the complete slave address is:
SNLS062G – NOVEMBER 2000 – REVISED JANUARY 2014
A6
A5
A4
A3
A2
A1
A0
MSB
LSB
and is selected as follows:
Address Select Pin
State
A2
A1
A0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
DS90C387R Serial
Bus Slave Address
A6:A0 binary
0111000
0111001
0111010
0111011
0111100
0111101
0111110
0111111
The DS90C387R latches the state of the address select pins during the first read or write on the Serial Bus.
Changing the state of the address select pins after the first read or write to any device on the Serial Bus will not
change the slave address of the DS90C387R.
A zero in front of the register address is required as the most left column shown in Table 4. For example, to
access register F, “0F” is the correct way of accessing the register.
Table 4. Register Mapping
Addr
000
001
002
003
004
005
006
007
008
009
00A
00B
00C
00D
00E
00F
Bit7
Bit6
Bit5
RSVD[1:0]
VEN(RW)
VLOW(RO)
MSEL[2:0](RW)
DK[3:1](RW) ⁽¹⁾
RSVD[3:0](RW)
Bit4
Bit3
VND_IDL(RO)
VND_IDH(RO)
DEV_IDL(RO)
DEV_IDH(RO)
DEV_REV(RO)
RSVD[7:0](RO)
FRQ_LOW[7:0](RO)
FRQ_HIGH[7:0](RO)
HEN(RW)
DSEL(RW)
TSEL(RW)
DKEN(RW) ⁽¹⁾
CFG[7:0](RO) ⁽¹⁾
VDJK[7:0](RW) ⁽¹⁾
RSVD[7:0](RW)
RSVD[7:0](RW)
(1) Features not implemented on DS90C387R
Bit2
Bit1
Bit0
BSEL(RW)
RSEN(RO)
CTL[3:1](RW)
EDGE(RW)
HTPLG(RO) ⁽¹⁾
PD(RW)
MDI(RW)
RSVD(RW)
RSVD[3:0](RO)
Field
VND_IDL
VND_IDH
DEV_IDL
DEV_IDH
DEV_REV
Access
RO
RO
RO
RO
RO
Table 5. Register Field Definitions
Vendor ID low byte, value is 05h.
Vendor ID high byte, value is 13h.
Device ID low byte, value is 24h.
Device ID high byte, value is 67h.
Device revision, value is 00h.
Description
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