DS90C387R_15 Datasheet, PDF (11/32 Pages) Texas Instruments – Dual 12-Bit Double Pumped Input LDI Transmitter - VGA/UXGA

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Pin Name
D0-D23
DE
HSYNC
VSYNC
AnP
AnM
CLKINP
CLKINM
R_FB
R_FDE
CLK1P
CLK1M
PD
PLLSEL
BAL
PRE
DUAL
V_CC
GND
I2V_CC
V_CC3V
GND_3V
SGND
PLLV_CC
PLLGND
LVDSV_CC
LVDSGND
CLK2P/NC
CLK2M/NC
DS90C387R
SNLS062G – NOVEMBER 2000 – REVISED JANUARY 2014
DS90C387R PIN DESCRIPTION—LDI TRANSMITTER
I/O
No.
Description
I
24
LVTTL level single-ended inputs or low swing pseduo differential inputs. Reference to V_REF pin.
D0-D11 are for 12-bit input mode (24 RGB data); D0-D11 (first 12-bit port) and D12-D23
(second 12-bit port) are for two 12-bit input mode (48 RGB data).
I
1
LVTTL level or low swing level inputs for data enable. This signal is HIGH when input pixel data
is valid to DS90C387R provided that R_FDE = HIGH.
I
1
Horizontal Sync input control signal. LVTTL level or low swing level.
I
1
Vertical Horizontal Sync input control signal. LVTTL level or low swing level.
O
8
Positive LVDS differential data output.
O
8
Negative LVDS differential data output.
I
1
In LVTTL level operation, this is a single-ended clock. In low swing operation, this is the positive
differential clock input .
I
1
In LVTTL level operation, no connect or connect to V_REF pin. Do not connect to GND under any
condition. In low swing operation, this is negative differential clock input .
I
1
LVTTL level input for selecting the Primary clock edge E1. Falling clock edge selected when
input is HIGH; Rising clock edge selected when input is LOW.⁽¹⁾
I
1
LVTTL level input. Programmable control (DE) strobe select. Tie HIGH for data active when DE
is HIGH. ⁽¹⁾
O
1
Positive LVDS differential clock output.
O
1
Negative LVDS differential clock output.
I
1
LVCMOS level input. Input = LOW will place the entire device in power down mode. Outputs of
the device will be in TRI-STATE mode to ensure low current at power down. ⁽¹⁾
Input = HIGH for normal operation.
I
1
LVTTL level in. Tie to Vcc for normal operation. ⁽¹⁾
I
1
LVTTL level input. Mode select for dc balanced or non-dc balanced interface. DC balance is
active when input is high. ⁽¹⁾
I
1
Pre-emphasis level select. Pre-emphasis is active when input is tied to V_CC through external
pull-up resistor. Resistor value determines pre-emphasis level (see table in application section).
For normal LVDS drive level (minimum pre-emphasis) leave this pin open (do not tie to
ground). ⁽¹⁾
I
1
LVTTL level input. Input = LOW for one 12-bit input mode, 24 RGB data in, 24 RGB data out. ⁽¹⁾
LVTTL level input. Input = V_CC for two 12-bit input mode, 48 RGB data in, 48 RGB data out.⁽¹⁾
I
1
Connect to power supply with voltage stated under Recommended Operating Conditions.
Power supply pin for LVTTL inputs and digital circuitry, pin53.
I
4
Ground pins for LVTTL inputs and digital circuitry, pins 9, 11, 52, 77.
I
1
Connect to power supply with voltage stated under Recommended Operating Conditions, pin
68.
I
3
Connect to power supply with voltage stated under Recommended Operating Conditions, pins
70, 79, 95.
I
3
Ground pin(s) for powering the data inputs, pins 71, 80, 96.
I
1
Connect to ground, pin 69.
I
2
Connect to power supply with voltage stated under Recommended Operating Conditions.
Power supply pins for PLL circuitry, pin 10, 16.
I
3
Ground pins for PLL circuitry, pins 14, 15, 17.
I
3
Connect to power supply with voltage stated under Recommended Operating Conditions.
Power supply pins for LVDS outputs, pins 30, 40, 48.
I
4
Ground pins for LVDS outputs, pins 25, 35, 43, 51.
O
1
Additional positive LVDS differential clock output identical to CLK1P. No connect if not used.
O
1
Additional negative LVDS differential clock output identical to CLK1M. No connect if not used.
(1) Inputs default to “low” when left open due to internal pull-down resistor.
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