DS90C387R_15 Datasheet, PDF (24/32 Pages) Texas Instruments – Dual 12-Bit Double Pumped Input LDI Transmitter - VGA/UXGA

DS90C387R
SNLS062G – NOVEMBER 2000 – REVISED JANUARY 2014
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Backwards Compatible Mode with FPD-Link
The transmitter provides a second LVDS output clock. Both LVDS clocks will be identical in 'Dual pixel mode'.
This feature supports backward compatibility with the previous generation of devices - the second clock allows
the transmitter to interface to panels using a 'dual pixel' configuration of two 24-bit or 18-bit 'notebook' receivers.
Pre-emphasis feature is available for use in both the DC balanced and non-DC balanced (backwards compatible)
modes.
Information on Jitter Rejection:
The transmitter is designed to reject cycle-to-cycle jitter which may be seen at the transmitter input clock. Very
low cycle-to-cycle jitter is passed on to the transmitter outputs. This significantly reduces the impact of jitter
provided by the input clock source, and improves the accuracy of data sampling. Data sampling is further
enhanced by automatically calibrated data sampling strobes at the receiver inputs. Timing and control signals
(VSYNC, HSYNC, DE) are sent during blanking intervals to guarantee correct reception of these critical signals.
The transmitter is offered with programmable primary clock edge for convenient interface with a variety of
graphics controllers. The transmitter can be programmed for rising edge strobe or falling edge strobe through a
dedicated pin. A rising edge transmitter will inter-operate with a falling edge receiver without any translation logic.
Transmitter Block Diagram
24
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