DS90C387R_15 Datasheet, PDF (22/32 Pages) Texas Instruments – Dual 12-Bit Double Pumped Input LDI Transmitter - VGA/UXGA

DS90C387R
SNLS062G – NOVEMBER 2000 – REVISED JANUARY 2014
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From DS90C387R
MSEN
To GMCH
INT#
2. To configure for single pixel application using the DS90C387R with single DS90CF384 or DS90CF384A or
DS90CF386 LVDS based LCD panel or monitor, the “DUAL” pin must be set to Gnd (single RGB), and “BAL” pin
must be set to Gnd to disable the feature for DS90CF384/DS90CF386 doesn't support DC balance function. For
cable length more than two meters, pre-emphasis feature is recommended. Please see table below for reference
pin connection.
From DS90C387R Output Pins To LVDS based LCD monitor
data signal connection
A0M
RxIN0−
A0P
RxIN0+
A1M
RxIN1−
A1P
RxIN1+
A2M
RxIN2−
A2P
RxIN2+
CLK1M
RxCLKIN0−
CLK1P
RxCLKIN0+
A3M(valid for 8-bit LCD only; no RxIN3−(valid for 8-bit LCD only; no
connect for 6-bit LCD)
connect for 6-bit LCD)
A3P(valid for 8-bit LCD only; no RxIN3+(valid for 8-bit LCD only; no
connect for 6-bit LCD)
connect for 6-bit LCD)
A4M
No connect
A4P
No connect
A5M
No connect
A5P
No connect
A6M
No connect
A6P
No connect
A7M
No connect
A7P
No connect
CLK2M
No connect
CLK2P
No connect
3. To configure for single pixel or dual pixel application using the DS90C387R with DS90CF388, the “DUAL” pin
must be set to Vcc (dual RGB) or Gnd (single RGB). Also, “BAL” pins on both devices have to in the same logic
state. For cable length more than two meters, pre-emphasis feature is recommended.
4. In dual mode, DS90C387R has two LVDS clock outputs enabling an interface to two FPD-Link 'notebook'
receivers (DS90CF384/DS90CF386). “BAL” pin must be set to Gnd to disable DC balance function for
DS90CF384/DS90CF386 doesn't support DC balance function. In single mode, outputs A4-to-A7 and CLK2 are
disabled which reduces power dissipation. For cable length more than two meters, pre-emphasis feature is
recommended.
The DS90CF388 is able to support single or dual pixel interface up to 112MHz operating frequency. This receiver
may also be used to interface to a VGA controller with an integrated LVDS transmitter without DC balance data
transmission. In this case, the receivers “BAL” pin must be tied low (DC balance disabled).
Features Description:
1. Pre-emphasis: adds extra current during LVDS logic transition to reduce the cable loading effects. Pre-
emphasis strength is set via a DC voltage level applied from min to max (0.75V to Vcc) at the “PRE” pin. A
higher input voltage on the ”PRE” pin increases the magnitude of dynamic current during data transition. The
“PRE” pin requires one pull-up resistor (Rpre) to Vcc in order to set the DC level. There is an internal resistor
network, which cause a voltage drop. Please refer to the tables below to set the voltage level.
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