DS90C387R_15 Datasheet, PDF (12/32 Pages) Texas Instruments – Dual 12-Bit Double Pumped Input LDI Transmitter - VGA/UXGA

DS90C387R
SNLS062G – NOVEMBER 2000 – REVISED JANUARY 2014
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Pin Name
V_REF
I2CSEL
DDREN/I2Cclk
DSEL/I2Cdat
A0
A1
A2
MSEN
TST1
TST2
RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
RESERVED6
RESERVED7
RESERVED8
RESERVED9
DS90C387R PIN DESCRIPTION—LDI TRANSMITTER (continued)
I/O
I
I
I
I/O
I
I
I
O
No.
Description
1
V_REF= 1/2 V_DDQ, a ”Fixed “ line of differential input.
If V_REF ≥ 1.8V, indicates input data is in LVTTL mode.
If V_REF < 1.1V, indicates input data is in low voltage swing mode.
In low voltage swing mode, input data = logic HIGH = V_REF + 100mV.
In low voltage swing mode, input data = logic LOW = V_REF - 100mV.
This pin is not to be left floating. When not use in LVTTL mode, tie to V_cc
1
HIGH to enable two-wire serial communication interface; LOW to disable the interface.
1
Always HIGH for one 12-bit port and two 12-bit ports operation. When I2CSEL = HIGH, this is
the clock line for the two-wire serial communication interface.
1
Differential select pin for CLKIN (HIGH = single-ended, LOW = differentail) or when I2CSEL =
HIGH, this is the Bidirectional Data line for the two-wire serial communication interface.
1
when I2CSEL = HIGH, this is one of the Slave Device Address Lower Bits.
1
when I2CSEL = HIGH, this is one of the Slave Device Address Lower Bits.
1
when I2CSEL = HIGH, this is one of the Slave Device Address Lower Bits.
1
Interrupt signal. This is an open drain output, pull-up resistor is required.
1
Test pin, tie to Vcc.
1
Test pin, no connect. Do not tie to ground.
1
Reserved pin, tie to ground.
1
Reserved pin, tie to ground.
1
Reserved pin, no connect. Do not tie to ground.
1
Reserved pin, tie to ground.
1
Reserved pin, tie to ground.
1
Reserved pin, tie to ground.
1
Reserved pin, tie to ground.
1
Reserved pin, tie to ground.
1
Reserved pin, tie to ground.
Table 2. Control Settings for mode selection
Mode
DUAL
BAL
I2CSEL
DDREN/I2Cclk
CLKIN polarity
CLKIN,single-ended/ differentail
Description
12bit
L
L/H
L
H
R_FB
DSEL
12-bit in, 24-bit pixel out, non-DC Balanced or
DC-Balanced
Two 12-bit
H
L/H
L
H
R_FB
DSEL
Two 12-bit in, two 24-bit pixels out, non-DC
Balanced or DC-Balanced.
R_FB
VCC
GND
Table 3. Relationship between R_FB, DE, HSYNC and VSYNC pins
Primary Edge
Falling
Rising
Secondary Edge
Rising
Falling
DE latches on
Rising
Falling
HSYNC latches on
Falling
Rising
VSYNC latches on
Falling
Rising
Two-Wire Serial Communication Interface Description
The DS90C387R operates as a slave on the Serial Bus, so the SCL line is an input (no clock is generated by the
DS90C387R) and the SDA line is bi-directional. DS90C387R has a 7-bit slave address. The address bits are
controlled by the state of the address select pins A2, A1 and A0, and are set by connecting these pins to ground
for a LOW, (0) , to V_CC for a HIGH, (1).
12
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