DS90C387R_15 Datasheet, PDF (15/32 Pages) Texas Instruments – Dual 12-Bit Double Pumped Input LDI Transmitter - VGA/UXGA

DS90C387R
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SNLS062G – NOVEMBER 2000 – REVISED JANUARY 2014
Communicating with the DS90C387R through Registers
There are 31 data registers in the DS90C387R, and can be accessed through sixteen register addresses. All
registers are predefined as read only, or read and write. The device will always attempt to detect if a LCD
panel/monitor is connected.
A Write to the DS90C387R will always include the slave address byte, data register address byte, a data byte.
Reading the DS90C387R can take place either of two ways:
1. If the location latched in the data register addresses is correct , then the read can simply consist of a slave
address byte, followed by retrieving the data byte.
2. If the data register address needs to be set, then a slave address byte, data register address will be sent
first, then the master will repeat start, send the slave address byte and data byte to accomplish a read.
The data byte has the most significant bit first. At the end of a read, the DS90C387R can accept either
Acknowledge or No Acknowledge from the Master (No Acknowledge is typically used as a signal for the slave
that the Master has read its last byte).
Two-Wire Serial Communication Interface for Slave
The DS90C387R slave state machine does not require an internal clock and it supports only byte read and write.
Page mode is not supported. The 7-bit binary address is “0111A₂A₁A₀”, where A₂A₁A₀ are pin programmable to “
1” or “ 0 ” and the “ 0111 ” is hardwired internally.
Figure 15. Byte Read
The master must generate a “ Start ” by sending the 7-bit slave address plus a 0 first, and wait for acknowledge
from DS90C387R. When DS90C387R acknowledges (the 1st ACK) that the master is calling, the master then
sends the data register address byte and waits for acknowledge from the slave. When the slave acknowledges
(the 2nd ACK), the master repeats the “ Start ” by sending the 7-bit slave address plus a 1 (indicating that READ
operation is in progress) and waits for acknowledge from DS90C387R. After the slave responds (the 3rd ACK),
the slave sends the data to the bus and waits for acknowledge from the master. When the master acknowledges
(the 4th ACK), it generates a “ Stop ”. This completes the “ READ ”.
Figure 16. Byte Write
The master must generate a “ Start ”, by sending the 7-bit slave address plus a 0 and wait for acknowledge from
DS90C387R. When DS90C387R acknowledges (the 1st ACK) that the master is calling, the master then sends
the data register address byte and waits for acknowledge from the slave. When the slave acknowledges (the 2nd
ACK), the master sends the data byte and wait for acknowledge from the slave. When the slave acknowledges
(the 3rd ACK), the master generates a “ Stop ”. This completes the “ WRITE ”.
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