LP3907_14 Datasheet, PDF (44/57 Pages) Texas Instruments – Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C-Compatible Interface

LP3907
SNVS511N – JUNE 2007 – REVISED AUGUST 2011
C_LDO1
C_LDO2
C_SW1
C_SW2
Capacitor
Min Value
0.47
0.47
10.0
10.0
Unit
Description
µF
LDO1 output capacitor
µF
LDO2 output capacitor
µF
SW1 output capacitor
µF
SW2 output capacitor
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Recommended Type
Ceramic, 6.3V, X5R
Ceramic, 6.3V, X5R
Ceramic, 6.3V, X5R
Ceramic, 6.3V, X5R
I²C Pullup Resistor
Both SDA and SCL terminals need to have pullup resistors connected to VINLDO12 or to the power supply of the
I²C master. The values of the pull-up resistors (typ. ∼1.8kΩ) are determined by the capacitance of the bus. Too
large of a resistor combined with a given bus capacitance will result in a rise time that would violate the max. rise
time specification. A too small resistor will result in a contention with the pull-down transistor on either slave(s) or
master.
Operation without I²C Interface
Operation of the LP3907 without the I²C interface is possible if the system can operate with default values for the
LDO and Buck regulators. (Read below: Factory programmable options). The I²C-less system must rely on the
correct default output values of the LDO and Buck converters.
Factory Programmable Options
The following options are EPROM programmed during final test of the LP3907. The system designer that needs
specific options is advised to contact the local National Semiconductor sales office.
Factory programmable options
Enable delay for power on
SW1 ramp speed
SW2 ramp speed
Current value
code 010 (see Control 1 register section)
8 mV/µs
8 mV/µs
The I²C Chip ID address is offered as a metal mask option. The current address for the LLP chip equals 0x60,
while the address for the micro SMD chip is 0x61.
HIGH V_IN HIGH-LOAD OPERATION
Additional information is provided when the IC is operated at extremes of V_IN and regulator loads. These are
described in terms of the Junction temperature and, Buck output ripple management.
JUNCTION TEMPERATURE
The maximum junction temperature T_J-MAX-OP of 125°C of the IC package.
The following equations demonstrate junction temperature determination, ambient temperature T_A-MAX and Total
chip power must be controlled to keep T_J below this maximum:
T^J-MAX-OP = T_A-MAX + (θ_JA) [°C/ Watt] * (P_D-MAX) [Watts]
Total IC power dissipation P_D-MAX is the sum of the individual power dissipation of the four regulators plus a minor
amount for chip overhead. Chip overhead is Bias, TSD & LDO analog.
P^D-MAX = P_LDO1 + P_LD02 + P_BUCK1 + P_BUCK2 + (0.0001A * V_IN) [Watts].
Power dissipation of LDO1
P_LDO1 = (V_INLDO1- V_OUTLDO1) * Iout_LDO1 [V*A]
Power dissipation of LDO2
P_LDO2 = (V_INLDO2 - Vout_LDO2) * Iout_LDO2 [V*A]
Power dissipation of Buck1
P_Buck1 = P_IN – P_OUT =
Vout_Buck1* Iout_Buck1 * (1 -η₁) / η₁ [V*A]
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