LP3907_14 Datasheet, PDF (32/57 Pages) Texas Instruments – Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C-Compatible Interface

LP3907
SNVS511N – JUNE 2007 – REVISED AUGUST 2011
ack from slave
ack from slave
ack from slave
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start msb Chip Address lsb w ack msb Register Add lsb ack msb DATA lsb ack stop
SCL
SDA
1 2 3 4 5 6 7 8 9 1 2 3 ...
start
id = K¶60
w ack
addr = K¶02
ack
DGGUHVV K¶$$ GDWD
w = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by either master or slave)
rs = repeated start
id = LP3907 LLP chip address: 0x60; micro SMD chip address: 0x61
Figure 14. I²C Write Cycle
ack stop
When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in
the Read Cycle waveform.
ack from slave
ack from slave repeated start
ack from slave data from slave ack from master
start msb Chip Address lsb w ack msb Register Add lsb ack rs msb Chip Address lsb r ack msb DATA lsb ack stop
SCL
.
SDA
start
id = K¶60
w ack register addr = K¶10 ack rs
id = K¶60
Figure 15. I²C Read Cycle
r ack
GDWD DGGU K¶6A
ack stop
LP3907 Control Registers
Register
Address
0x02
0x07
0x10
0x11
0x20
0x23
0x24
0x25
0x29
0x2A
0x2B
0x38
0x39
0x3A
Register
Name
ICRA
SCR1
BKLDOEN
BKLDOSR
VCCR
B1TV1
B1TV2
B1RC
B2TV1
B2TV2
B2RC
BFCR
LDO1VCR
LDO2VCR
Read/Write
Register Description
R
Interrupt Status Register A
R/W System Control 1 Register
R/W Buck and LDO Output Voltage Enable Register
R
Buck and LDO Output Voltage Status Register
R/W Voltage Change Control Register 1
R/W Buck1 Target Voltage 1 Register
R/W Buck1 Target Voltage 2 Register
R/W Buck1 Ramp Control
R/W Buck2 Target Voltage 1 Register
R/W Buck2 Target Voltage 2 Register
R/W Buck2 Ramp Control
R/W Buck Function Register
R/W LDO1 Voltage control Registers
R/W LDO2 Voltage control Registers
32
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