LP3907_14 Datasheet, PDF (10/57 Pages) Texas Instruments – Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C-Compatible Interface

LP3907
SNVS511N – JUNE 2007 – REVISED AUGUST 2011
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Low Drop Out Regulators, LDO1 and LDO2
Unless otherwise noted, V_IN = 3.6V, C_IN = 1.0µF, C_OUT = 0.47µF. Typical values and limits appearing in normal type apply for
T_J = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40°C to
+125°C. ^{(1) (2) (3) (4) (5) (6) (7)}
Symbol
Parameter
Conditions
Min
Typ
Max Units
V_IN
Operational Voltage Range
VINLDO1 and VINLDO2 PMOS
pins ⁽⁸⁾
1.74
5.5
V
V_OUT Accuracy Output Voltage Accuracy (Default V_OUT) Load current = 1 mA
−3
ΔV_OUT
Line Regulation
V_IN = (V_OUT + 0.3V) to 5.0V,
(7)_{, Load Current = mA}
3
%
0.15
%/V
I_SC
V_IN – V_OUT
Load Regulation
Short Circuit Current Limit
Dropout Voltage
V_IN = 3.6V,
Load Current = 1mA to I_MAX
LDO1-2, V_OUT = 0V
Load Current = 50mA
(5)
0.011 %/mA
500
mA
30
200
mV
PSRR
θn
I_Q ^{(6) (9)}
T_ON
C_OUT
Power Supply Ripple Rejection
Supply Output Noise
Quiescent Current “On”
Quiescent Current “On”
Quiescent Current “Off”
Turn On Time
Output Capacitor
F = 10kHz, Load Current = I_MAX
10Hz < F < 100KHz
I_OUT = 0mA
I_OUT = I_MAX
EN is de-asserted⁽¹⁰⁾
Start up from shut-down
Capacitance for stability 0°C ≤ T_J
≤ 125°C
−40°C ≤ T_J ≤ 125°C
ESR
0.33
0.68
5
45
80
40
60
0.03
300
0.47
1.0
dB
µVrms
µA
µA
µA
µs
µF
µF
500
mΩ
(1) All voltages are with respect to the potential at the GND pin.
(2) Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the
most likely norm.
(3) C_IN, C_OUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.
(4) The device maintains a stable, regulated output voltage without a load.
(5) Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100mV below its nominal
value.
(6) Quiescent current is defined here as the difference in current between the input voltage source and the load at V_OUT.
(7) V_IN minimum for line regulation values is 1.8V.
(8) Pins 24, 19 can operate from V_IN min of 1.74 to a V_IN max of 5.5V. This rating is only for the series pass PMOS power FET. It allows the
system design to use a lower voltage rating if the input voltage comes from a buck output.
(9) The I_Q can be defined as the standing current of the LP3907 when the I²C bus is active and all other power blocks have been disabled
via the I²C bus, or it can be defined as the I²C bus active, and the other power blocks are active under no load condition. These two
values can be used by the system designer when the LP3907 is powered using a battery.
(10) The I_Q exhibits a higher current draw when the EN pin is de-asserted because the I²2 buffer pins draw an additional 2µA.
10
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