LP3907_14 Datasheet, PDF (25/57 Pages) Texas Instruments – Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C-Compatible Interface

LP3907
www.ti.com
SNVS511N – JUNE 2007 – REVISED AUGUST 2011
POWER UP SEQUENCING USING THE EN_T FUNCTION
EN_T assertion causes the LP3907 to emerge from Standby mode to Full Operation mode at a preset timing
sequence. By default, the enables for the LDOs and Bucks (ENLDO1, ENLDO2, EN_T, ENSW1, ENSW2) are
500K internally pulled down, which causes the part to stay OFF until enabled. If the user wishes to use the
preset timing sequence to power on the regulators, transition the EN_T pin from Low to High. Otherwise, simply
tie the enables of each specific regulator HIGH to turn on automatically.
EN_T is edge triggered with rising edge signaling the chip to power on. The EN_T input is deglitched and the
default is set at 1ms. As shown in the next 2 diagrams, a rising EN_T edge will start a power-on sequence, while
a falling EN_T edge will start a shutdown sequence. If EN_T is high, toggling the external enables of the
regulators will have no effect on the chip.
The regulators can also be programmed through I²C to turn on and off. By default, I²C enables for the regulators
on ON.
The regulators are on following the pattern below:
Regulators on = (I²C enable) AND (External pin enable OR EN_T high).
Note: The EN_T power-up sequencing may also be employed immediately after V_IN is applied to the device.
However, V_IN must be stable for approximately 8ms minimum before EN_T be asserted high to ensure internal
bias, reference, and the Flexible POR timing are stabilized. This initial EN_T delay is necessary only upon first
time device power on for power sequencing function to operate properly.
I²C
Regulator ON
Ext_Enable
Pins
0
1
Start Programmed
Timing Sequence
EN_T
LP3907 Default Power-Up Sequence
EN_T
Vout Buck1
Vout Buck2
t₁
t₂
Vout LDO1
Vout LDO2
t₃
t₄
Table 4. Power-On Timing Specification
Symbol
t₁
t₂
t₃
t₄
Description
Programmable Delay from EN_T assertion to V_CC_Buck1 On
Programmable Delay from EN_T assertion to V_CC_Buck2 On
Programmable Delay from EN_T assertion to V_CC_LDO1 On
Programmable Delay from EN_T assertion to V_CC_LDO2 On
Min
Typ
Max
Units
1.5
ms
2
ms
3
ms
6
ms
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