LP3907_14 Datasheet, PDF (24/57 Pages) Texas Instruments – Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C-Compatible Interface

LP3907
SNVS511N – JUNE 2007 – REVISED AUGUST 2011
www.ti.com
PFM Mode at Light Load
Load current
increases
High PFM Threshold
~1.016 * Vout
Low1 PFM Threshold
~1.008 * Vout
Pfet on
until
Ipfm limit
reached
Nfet on
drains
inductor
current
until
I inductor = 0
High PFM
Voltage
Threshold
reached,
go into
sleep mode
Low PFM
Threshold,
turn on
PFET
Current load
increases,
draws Vout
towards
Low2 PFM
Threshold
Low2 PFM Threshold
Vout
Low2 PFM Threshold,
switch back to PWMmode
PWM Mode at
Moderate to Heavy
Loads
SHUTDOWN MODE
During shutdown the PFET switch, reference, control and bias circuitry of the converters are turned off. The
NFET switch will be on in shutdown to discharge the output. When the converter is enabled, soft start is
activated. It is recommended to disable the converter during the system power up and under voltage conditions
when the supply is less than 2.8V.
SOFT START
The soft-start feature allows the power converter to gradually reach the initial steady state operating point, thus
reducing startup stresses and surges. The two LP3907 buck converters have a soft-start circuit that limits in-rush
current during startup. During startup the switch current limit is increased in steps. Soft start is activated only if
EN goes from logic low to logic high after V_IN reaches 2.8V. Soft start is implemented by increasing switch
current limit in steps of 180mA, 300mA, and 720mA for Buck1; 161mA, 300mA and 536mA for Buck2 (typ.
Switch current limit). The start-up time thereby depends on the output capacitor and load current demanded at
start-up.
LOW DROPOUT OPERATION
The LP3907 can operate at 100% duty cycle (no switching; PMOS switch completely on) for low drop out support
of the output voltage. In this way the output voltage will be controlled down to the lowest possible input voltage.
When the device operates near 100% duty cycle, output voltage ripple is approximately 25mV. The minimum
input voltage needed to support the output voltage is
V_{IN, MIN} = I_LOAD * (R_{DSON, PFET} + R_INDUCTOR) + V_OUT
• I_LOAD
• R_{DSON, PFET}
• R_INDUCTOR
Load current
Drain to source resistance of
PFET switch in the triode region
Inductor resistance
FLEXIBLE POWER SEQUENCING OF MULTIPLE POWER SUPPLIES
The LP3907 provides several options for power on sequencing. The two bucks can be individually controlled with
ENSW1 and ENSW2. The two LDOs can also be individually controlled with ENLDO1 and ENLDO2.
If the user desires a set power on sequence, he can program the chip through I²C and raise EN_T from LOW to
HIGH to activate the power on sequencing.
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