TMDS261B Datasheet, PDF (41/48 Pages) Texas Instruments – TWO-PORT HDMI SWITCH

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TMDS261B
SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011
Register 0x01 is read/write.
Table 9. I²C Register 0x02 Lookup Table
BIT VALUE STATE DEFAULT
7:6 Bit 7 Bit 6
1
1
X
1
0
0
0
0
1
5:4 Bit 4 Bit 3
0
0
0
1
X
1
1
3:2 Bit 3 Bit 2
1
1
1
0
0
1
0
0
X
1:0 Bit 1 Bit 0
1
0
1
1
0
1
0
0
X
Register 0x02 is read-only.
DESCRIPTION
Port Select Status Indicator
Indicates port 1 is selected as the active port, all other ports are low.
Indicates port 2 is selected as the active port, all other ports are low.
Disallowed (indeterminate state, all terminations are disconnected)
Indicates standby mode: HPD[1:2] follows HPD_SINK.
OVS Control Status Indicator
Indicates DDC sink side V_OL and V_IL offset range 2: V_{IL2 (max)}: 0.4 V, V_{OL2 (max)}: 0.6 V
Indicates DDC sink side V_OL and V_IL offset range 3: V_{IL3 (max)}: 0.3 V, V_{OL3 (max)}: 0.5 V
Indicates DDC sink side V_OL and V_IL offset range 1: V_{IL1 (max)}: 0.4 V, V_{OL1 (max)}: 0.7 V
Output Edge Rate Status Control
Indicates fastest TMDS output rise and fall time setting + 120 ps approximately (slowest rise
and fall time setting)
Indicates fastest TMDS output rise and fall time setting + 100 ps approximately
Indicates fastest TMDS output rise and fall time setting + 50 ps approximately
Indicates fastest TMDS output rise and fall time setting
Power-Mode Status Indicator
Indicates device enters low-power mode
Indicates device enters low-power mode
Reserved
Indicates device is in normal-power mode
Table 10. I²C Register 0x03 Lookup Table
BIT VALUE STATE DEFAULT
DESCRIPTION
7
1
Clock
detect
disabled
Clock-detect circuit disabled. For HDMI compliance testing (TMDS termination-voltage test),
clock-detect feature should be disabled. In this mode, the terminations on the TMDS input data
lines are always connected when the port is selected.
0
Clock
detect
enabled
X
Clock-detect circuit enabled. It is recommended that the TMDS261B is used in this default
mode during normal operation where clock detect circuit is enabled. The terminations on the
TMDS input data lines are connected only when a valid TMDS clock is detected on the selected
port.
6:5
X
RSVD
Reserved
4
0
RSVD
X
Note: Do not write a 1 to this bit.
3:0
0
RSVD
X
Reserved
Register 0x03 is read/write. For disabling clock detect, the value of 80h or 1000 0000b can be written to register
0x03.
Table 11. I²C Register 0x04 Lookup Table
BIT VALUE STATE DEFAULT
DESCRIPTION
7
1
Clock
detected
A valid clock signal is detected on the selected port. If clock detect is disabled in register
0x03, then bit 7 of register 0x04 is always 1.
0
No clock
detect
X
The selected port does not have a valid clock signal.
6:5
X
RSVD
Reserved
4
0
RSVD
X
This bit should always read 0
3:0
0
RSVD
X
Reserved
Copyright © 2009–2011, Texas Instruments Incorporated
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