TMDS261B Datasheet, PDF (36/48 Pages) Texas Instruments – TWO-PORT HDMI SWITCH

TMDS261B
SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011
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GENERAL I²C PROTOCOL
• The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 50. All I²C-compatible devices should
recognize a start condition.
• The master then generates the SCL pulses and transmits the 7-bit address and the read/write direction bit
R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition
requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 51). All devices
recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave
device with a matching address generates an acknowledge (see Figure 52) by driving the SDA line low during
the entire high period of the ninth SCL cycle. On detecting this acknowledge, the master knows that a
communication link with a slave has been established.
• The master generates further SCL cycles to either transmit data to the slave (R/W bit 0) or receive data from
the slave (R/W bit 1). In either case, the receiver must acknowledge the data sent by the transmitter. So an
acknowledge signal can be generated either by the master or by the slave, depending on which one is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long
as necessary (See Figure 54 through Figure 57).
• To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low
to high while the SCL line is high (see Figure 50). This releases the bus and stops the communication link
with the addressed slave. All I²C compatible devices must recognize the stop condition. Upon the receipt of a
stop condition, all devices know that the bus is released, and they wait for a start condition followed by a
matching address.
SDA
SCL
Data Line
Stable;
Data Valid
Change of Data Allowed
T0394-01
Figure 51. I²C Bit Transfer
Data Output
by Transmitter
Data Output
by Receiver
SCL From
Master
S
START
Condition
Not Acknowledge
1
2
Figure 52. I²C Acknowledge
Acknowledge
8
9
Clock Pulse for
Acknowledgement
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