TMDS261B Datasheet, PDF (16/48 Pages) Texas Instruments – TWO-PORT HDMI SWITCH

TMDS261B
SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011
www.ti.com
SWITCHING CHARACTERISTICS (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP⁽¹⁾ MAX UNIT
t_JITC(PP)
Peak-to-peak output residual clock jitter
AVCC = 3.3 V, R_T = 50 Ω, input TMDS clock
frequency = 225 MHz. See Figure 14for
measurement setup; residual jitter is the total
jitter measured at TTP4 minus the jitter
measured at TTP1. See Figure 15 for the loss
profile of the cable used for t_JITC(PP)
measurement. t_JITC(PP) is measured at TMDS
differential clock signal crossing.
54
84 ps
t_CLK1
Valid clock-detect enable time
AVCC = 3.3 V, R_T = 50 Ω, input TMDS clock
frequency = 300 MHz. See Figure 13.
300
500 ns
t_CLK2
t_SEL1
t_SEL2
f_CD
Invalid clock-detect disable time
Port selection time (see ⁽⁴⁾
Port deselection time (see ⁽⁵⁾)
Clock-detect frequency
AVCC = 3.3 V, R_T = 50 Ω, input TMDS clock
frequency = 1 MHz. See Figure 13.
AVCC = 3.3 V, R_T = 50 Ω
AVCC = 3.3 V, R_T = 50 Ω
AVCC = 3.3 V, R_T = 50 Ω. See Figure 13.
500
800 ns
300
500 ns
40
50 ns
25
300 MHz
(4) t_SEL1 includes the time for the valid clock-detect enable time and t_S1(HPD), because the t_S1(HPD) event happens in parallel with t_SEL1; thus,
the t_SEL1 time is primarily the t_CLK1 time.
(5) t_SEL2 is primarily the t_S2(HPD) time.
VCC
AVCC
50 W
50 W
D+
V_D+ ^VID
D–
V_D–
Receiver
V_ID = V_D+ – V_D–
V_ICM = ^(VD+ ^{+ V}D–⁾
2
Driver
Y
Z
V_OD = V_Y – V_Z
V_OC = ^(VY ^{+ V}Z⁾
2
50 W
0.5 pF
V_Y
V_Z
50 W
Figure 9. TMDS Main-Link Test Circuit
S0371-02
16
Copyright © 2009–2011, Texas Instruments Incorporated