TMDS261B Datasheet, PDF (39/48 Pages) Texas Instruments – TWO-PORT HDMI SWITCH

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Data is the register address or register data to be written
Step 7
8
I²C acknowledge (slave)
A
TMDS261B
SLLS987A – SEPTEMBER 2009 – REVISED JULY 2011
Step 8
0
I²C stop (master)
P
An example of the proper bit control for selecting port 2 is:
Step 4: 0000 0001
Step 6: 1001 0000
EXAMPLE – READING FROM THE TMDS261B
The read operation consists of two phases. The first phase is the address phase. In this phase, an I²C master
initiates a write operation to the TMDS261B by generating a start condition (S) followed by the TMDS261B I²C
address, in MSB-first bit order, followed by a 0 to indicate a write cycle. After receiving acknowledges from the
TMDS261B, the master presents the subaddress of the register to be read. After the cycle is acknowledged (A),
the master may optionally terminate the cycle by generating a stop condition (P).
The second phase is the data phase. In this phase, an I²C master initiates a read operation to the TMDS261B by
generating a start condition followed by the TMDS261B I²C address (as shown following for a read operation), in
MSB first bit order, followed by a 1 to indicate a read cycle. After an acknowledge from the TMDS261B, the I²C
master receives one byte of data from the TMDS261B. The master can continue receiving data byes by issuing
an acknowledge after each byte read (steps 10, 11). After the last data byte has been transferred from the
TMDS261B to the master, the master generates a not-acknowledge followed by a stop.
TMDS261B Read Phase 1
Step 1
0
I²C start (master)
S
Step 2
I²C general address (master)
7
6
5
4
3
2
1
0
0
1
0
1
1
0
0
0
Step 3
8
I²C acknowledge (slave)
A
Step 4
7
6
5
4
3
2
1
0
I²C write sink logic address (master)
0
0
0
0
Addr
Addr
Addr
Addr
Where Addr is determined by the values shown in Table 7.
Step 5
8
I²C acknowledge (slave)
A
Step 6
0
I²C stop (master)
P
Step 6 is optional.
TMDS261B Read Phase 2
Step 7
0
I²C start (master)
S
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