LP3971 Datasheet, PDF (41/57 Pages) National Semiconductor (TI) – POWER MANAGEMENT UNIT FOR ADVANCED APPLICATION PROCESSORS

LP3971
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POWER-ON TIMING
Symbol
t1
t2
t3
t4
t5
Description
Delay from V_CC_RTC assertion to nRSTO de-assertion
Delay from nBATT_FLT de-assertion to nRSTI assertion
Delay from nRST de-assertion to SYS_EN assertion
Delay from SYS_EN assertion to PWR_EN assertion
Delay from PWR_EN assertion to nRSTO de-assertion
SNVS432U – JANUARY 2006 – REVISED OCTOBER 2008
Min
Typ
Max Units
50
mS
100
µS
10
mS
125
mS
125
mS
HARDWARE RESET SEQUENCE
Hardware reset initiates when the nRSTI signal is asserted (low). Upon assertion of nRST the processor enters
hardware reset state. The LP3971 holds the nRST low long enough (50 ms typ.) to allow the processor time to
initiate the reset state.
RESET SEQUENCE
1. nRSTI is asserted.
2. nRSTO is asserted and will de-asserts after a minimum of 50 mS
3. The Applications processor waits for the de-assertion of nBATT_FLT to indicate system power (V_IN) is
available.
4. After system power (V_IN) is turned on, the LP3971 de-asserts nBATT_FLT.
5. The Applications processor asserts SYS_EN, the LP3971 enables the system high-voltage power supplies.
The Applications processor starts its countdown timer.
6. The LP3971 enables the high-voltage power supplies.
7. Countdown timer expires; the Applications processor asserts PWR_EN to enable the low-voltage power
supplies. The processor starts the countdown timer.
8. The Applications processor asserts PWR_EN, the LP3971 enables the low-voltage regulators.
9. Countdown timer expires; If enabled power domains are OK (I²C read) the power up sequence continues by
enabling the processors 13 MHz oscillator and PLL’s.
10. The Applications processor begins the execution of code.
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