LP3971 Datasheet, PDF (4/57 Pages) National Semiconductor (TI) – POWER MANAGEMENT UNIT FOR ADVANCED APPLICATION PROCESSORS

LP3971
SNVS432U – JANUARY 2006 – REVISED OCTOBER 2008
Connection Diagrams and Package Mark Information
Figure 1. 40-Pin Leadless Leadframe Package
30 29 28 27 26 25 24 23 22 21
21 22 23 24 25 26 27 28 29 30
31
20
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40
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Top View
Note: Circle marks pin 1 position.
10 9 8 7 6 5 4 3 2 1
Bottom View
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UZYYTT
71-XXXX
Note: The actual physical placement of the package marking will vary from part to part.
(*) UZTTY format: 'U' — wafer fab code; 'Z' _ assembly code; 'XY' 2 digit date code; 'TT' _ die run code.
See http://www.national.com/quality/marking_conventions.html for more information on marking information.
Figure 2. Package Mark
Top View
Z
0
1
2
3
4
5
6
7
8
9
A
4
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Default V_OUT Coding
Default V_OUT
1.3
1.8
2.5
2.8
3.0
3.3
1.0
1.4
1.2
1.25
1.35
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