LP3971 Datasheet, PDF (22/57 Pages) National Semiconductor (TI) – POWER MANAGEMENT UNIT FOR ADVANCED APPLICATION PROCESSORS

LP3971
SNVS432U – JANUARY 2006 – REVISED OCTOBER 2008
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I²C START AND STOP CONDITIONS
START and STOP bits classify the beginning and the end of the I²C session. START condition is defined as SDA
signal transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA
transitioning from LOW to HIGH while SCL is HIGH. The I²C master always generates START and STOP bits.
The I²C bus is considered to be busy after START condition and free after STOP condition. During data
transmission, I²C master can generate repeated START conditions. First START and repeated START
conditions are equivalent, function-wise.
SDA
SCL
S
START condition
P
STOP condition
TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.
The number of bytes that can be transmitted per transfer is unrestricted. Each byte of data has to be followed by
an acknowledge bit. The acknowledge related clock pulse is generated by the master. The transmitter releases
the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the
9th clock pulse, signifying an acknowledge. A receiver which has been addressed must generate an
acknowledge after each byte has been received.
After the START condition, a chip address is sent by the I²C master. This address is seven bits long followed by
an eighth bit which is a data direction bit (R/W). The LP3971 address is 34h. For the eighth bit, a “0” indicates a
WRITE and a “1” indicates a READ. The second byte selects the register to which the data will be written. The
third byte contains data to write to the selected register.
I²C CHIP ADDRESS - 7h'34
MSB
ADR6
ADR5
ADR4
ADR3
ADR2
ADR1
ADR0
R/W
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0
1
1
0
1
0
0
R/W
Write Cycle
Figure 7. Write cycle
start msb Chip Address lsb w ack Msb Register Add lsb ack msb DATA lsb
ack stop
SCL
SDA
start
Id = 34h
w ack
addr = 02h
ack
DGGUHVV K¶02 data
ack stop
Read Cycle
When a READ function is to be accomplished, a WRITE function must precede the READ function as follows.
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