LP3971 Datasheet, PDF (40/57 Pages) National Semiconductor (TI) – POWER MANAGEMENT UNIT FOR ADVANCED APPLICATION PROCESSORS

LP3971
SNVS432U – JANUARY 2006 – REVISED OCTOBER 2008
Application Note - LP3971 Reset Sequence
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INITIAL COLD START POWER ON SEQUENCE
1. The Back up battery is connected to the PMU, power is applied to the back-up battery pin, the RTC_LDO
turns on and supplies a stable output voltage to the V_CC_BATT pin of the Applications processor (initiating
the power-on reset event) with nRSTO asserted from the LP3971 to the processor.
2. nRSTO de-asserts after a minimum of 50 mS.
3. The Applications processor waits for the de-assertion of nBATT_FLT to indicate system power (V_IN) is
available.
4. After system power (V_IN) is applied, the LP3971 de-asserts nBATT_FLT. Note that BOTH nRSTO and
nBATT_FLT need to be de-asserted before SYS_EN is enabled. The sequence of the two signals is
independent of each other.
5. The Applications processor asserts SYS_EN, the LP3971 enables the system high-voltage power supplies.
The Applications processor starts its countdown timer set to 125 mS.
6. The LP3971 enables the high-voltage power supplies.
– LDO1 power for V_CC_MVT (Power for internal logic and I/O Blocks), BG (Bandgap reference voltage),
OSC13M (13 MHz oscillator voltage) and PLL enabled first, followed by others if delay is on.
7. Countdown timer expires; the Applications processor asserts PWR_EN to enable the low-voltage power
supplies. The processor starts the countdown timer set to 125 mS period.
8. The Applications processor asserts PWR_EN (ext. pin or I²C), the LP3971 enables the low-voltage
regulators.
9. Countdown timer expires; If enabled power domains are OK (I²C read) the power up sequence continues by
enabling the processors 13 MHz oscillator and PLL’s.
10. The Applications processor begins the execution of code.
t₁
t₃
t₄
V_IN BU Batt
1.
VCC_RTC
nRSTO
2.
V_IN Main Batt
nBATT_FLT
3,4.
SYS_EN
High-Volt_PD
PWR_EN
Low-Volt_PD
nRESET_OUT
PXA27x Output
5.
6.
PXA27x Output
t₂
PXA27x Output
7.
8.
t₅
13 MHZ_OSC
PXA27x Output
9,10.
Note that BOTH nRSTO and nBATT_FLT need to be de-asserted before SYS_EN is enabled. The sequence of the
two signals is independent of each other and can occur is either order.
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