LP3971 Datasheet, PDF (20/57 Pages) National Semiconductor (TI) – POWER MANAGEMENT UNIT FOR ADVANCED APPLICATION PROCESSORS

LP3971
SNVS432U – JANUARY 2006 – REVISED OCTOBER 2008
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PFM Mode at Light Load
Pfet on
until
Ipfm limit
reached
Nfet on
drains
conductor
current
until
I inductor=0
High PFM
Voltage
Threshold
reached,
go into
sleep mode
Low PFM
Threshold,
turn on
PFET
High PFM Threshold
~1.017*Vout
Load current
increases
Current load
increases,
draws Vout
towards
Low2 PFM
Threshold
Low1 PFM Threshold
~1.006*Vout
Low2 PFM Threshold
Vout
Low2 PFM Threshold,
switch back to PWMmode
PWM Mode at
Moderate to Heavy
Loads
Figure 5. Operation in PFM Mode and Transfer to PWM Mode
SHUTDOWN MODE
During shutdown the PFET switch, reference, control and bias circuitry of the converters are turned off. The
NFET switch will be open in shutdown to discharge the output. When the converter is enabled, EN, soft start is
activated. It is recommended to disable the converter during the system power up and undervoltage conditions
when the supply is less than 2.7V.
SOFT START
The buck converter has a soft-start circuit that limits in-rush current during start-up. During start-up the switch
current limit is increased in steps. Soft start is activated only if EN goes from logic low to logic high after V_IN
reaches 2.7V. Soft start is implemented by increasing switch current limit in steps of 213 mA, 425 mA, 850 mA
and 1700 mA (typ. Switch current limit). The start-up time thereby depends on the output capacitor and load
current demanded at start-up. Typical start-up times with 10 μF output capacitor and 1000 mA load current is 390
μs and with 1 mA load current is 295 μs.
LDO - LOW DROP OUT OPERATION
The LP3971 can operate at 100% duty cycle (no switching; PMOS switch completely on) for low drop out support
of the output voltage. In this way the output voltage will be controlled down to the lowest possible input voltage.
When the device operates near 100% duty cycle, output voltage ripple is approximately 25 mV. The minimum
input voltage needed to support the output voltage is
V_{IN, MIN} = I_LOAD * (R_{DSON, PFET} + R_INDUCTOR) + V_OUT
(1)
I_LOAD
R_{DSON, PFET}
R_INDUCTOR
Load Current
Drain to source resistance of PFET switch in the triode region
Inductor resistance
20
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