LP3971 Datasheet, PDF (21/57 Pages) National Semiconductor (TI) – POWER MANAGEMENT UNIT FOR ADVANCED APPLICATION PROCESSORS

LP3971
www.ti.com
SNVS432U – JANUARY 2006 – REVISED OCTOBER 2008
SPREAD SPECTRUM FEATURE
Periodic switching in the buck regulator is inherently a noisier function block compared to an LDO. It can be
challenging in some critical applications to comply with stringent regulatory standards or simply to minimize
interference to sensitive circuits in space limited portable systems. The regulator’s switching frequency and
harmonics can cause “noise” in the signal spectrum. The magnitude of this noise is measured by its power
spectral density. The power spectral density of the switching frequency, F_C, is one parameter that system
designers want to be as low as practical to reduce interference to the environment and subsystems within their
products. The LP3971 has a user selectable function on chip, wherein a noise reduction technique known as
“spread spectrum” can be employed to ease customer’s design and production issues.
The principle behind spread spectrum is to modulate the switching frequency slightly and slowly, and spread the
signal frequency over a broader bandwidth. Thus, its power spectral density becomes attenuated, and the
associated interference electro-magnetic energy is reduced. The clock used to modulate the LP3971 buck
regulator can be used as a spread spectrum clock via 2 I²C control register (System Control Register 1 (SCR1)
8h’80) bits bk_ssen, and slomod. With this feature enabled, the intense energy of the clock frequency can be
spread across a small band of frequencies in the neighborhood of the center frequency. This results in a
reduction of the peak energy!
The LP3971 spread spectrum clock uses a triangular modulation profile with equal rise and fall slopes. The
modulation has the following characteristics:
• The center frequency: F_C = 2 MHz, and
• The modulating frequency, f_M = 6.8 kHz or 12 kHz.
• Peak frequency deviation: Δ_f = ±100 kHz (or ±5%)
• Modulation index β = Δ_f/f_M = 14.7 or 8.3
Figure 6. Switching Energy RBW = 300 Hz
0
-10
-20
-30
-40
-50
-60
2040
2060 2080 2100 2120
FREQUENCY (kHz)
2140
I²C Compatible Interface
I²C DATA VALIDITY
The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of
the data line can only be changed when CLK is LOW.
SCL
SDA
data
change
allowed
data valid
data
change
allowed
data valid
data
change
allowed
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