DAC8551IADGKRG4 Datasheet, PDF (4/26 Pages) Texas Instruments – 16-BIT, ULTRA-LOW GLITCH, VOLTAGE OUTPUT

DAC8551
SLAS429B – APRIL 2005 – REVISED OCTOBER 2006
PIN CONFIGURATION
DGK PACKAGE
MSOP-8
(Top View)
V_{DD 1}
V_{REF 2}
V_{FB 3}
V_{OUT 4}
DAC8551
8 ^GND
7 ^DIN
6 ^SCLK
5 ^SYNC
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PIN DESCRIPTIONS
PIN NAME
DESCRIPTION
1
V_DD Power supply input, 2.7V to 5.5V.
2 V_REF Reference voltage input.
3
V_FB Feedback connection for the output amplifier. For voltage output operation, tie to V_OUT externally.
4 V_OUT Analog output voltage from DAC. The output amplifier has rail-to-rail operation.
Level-triggered control input (active LOW). This is the frame synchronization signal for the input data. When SYNC goes
5
SYNC
LOW, it enables the input shift register and data is transferred in on the falling edges of the following clocks. The DAC is
updated following the 24th clock (unless SYNC is taken HIGH before this edge, in which case the rising edge of SYNC
acts as an interrupt and the write sequence is ignored by the DAC8551). Schmitt-Trigger logic input.
6 SCLK Serial clock input. Data can be transferred at rates up to 30MHz. Schmitt-Trigger logic input.
7
D_IN
Serial data input. Data is clocked into the 24-bit input shift register on each falling edge of the serial clock input.
Schmitt-Trigger logic input.
8 GND Ground reference point for all circuitry on the part.
4
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