DAC8551IADGKRG4 Datasheet, PDF (17/26 Pages) Texas Instruments – 16-BIT, ULTRA-LOW GLITCH, VOLTAGE OUTPUT

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POWER-DOWN MODES
The DAC8551 supports four separate modes of
operation. These modes are programmable by
setting two bits (PD1 and PD0) in the control
register. Table 1 shows how the state of the bits
corresponds to the mode of operation of the device.
PD1
(DB17)
0
–
0
1
1
Table 1. Operating Modes
PD0
(DB16)
0
–
1
0
1
OPERATING MODE
Normal operation
Power-down modes
Output typically 1kΩ to GND
Output typically 100kΩ to GND
High-Z
When both bits are set to '0', the device works
normally with its typical current consumption of
200µA at 5V. However, for the three power-down
modes, the supply current falls to 200nA at 5V (50nA
at 3V). Not only does the supply current fall, but the
output stage is also internally switched from the
output of the amplifier to a resistor network of known
values. This configuration has the advantage that the
output impedance of the device is known while it is in
DAC8551
SLAS429B – APRIL 2005 – REVISED OCTOBER 2006
power-down mode. There are three different options.
The output is connected internally to GND through a
1kΩ resistor, a 100kΩ resistor, or it is left
open-circuited (High-Z). The output stage is
illustrated in Figure 49.
V_FB
Resistor
String
DAC
Amplifier
Power-Down
Circuitry
V_OUT
Resistor
Network
Figure 49. Output Stage During Power-Down
All analog circuitry is shut down when the
power-down mode is activated. However, the
contents of the DAC register are unaffected when in
power-down. The time to exit power-down is typically
2.5µs for V_DD = 5V, and 5µs for V_DD = 3V. See the
Typical Characteristics for more information.
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