DAC8551IADGKRG4 Datasheet, PDF (15/26 Pages) Texas Instruments – 16-BIT, ULTRA-LOW GLITCH, VOLTAGE OUTPUT

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DAC8551
THEORY OF OPERATION
SLAS429B – APRIL 2005 – REVISED OCTOBER 2006
DAC SECTION
The DAC8551 architecture consists of a string DAC
followed by an output buffer amplifier. Figure 45
shows a block diagram of the DAC architecture.
DAC
Register
V_REF
50kW
62kW
REF (+)
Register String
REF (-)
50kW
V_FB
V_OUT
V_REF
R_DIVIDER
V_REF
2
R
R
To Output Amplifier
(2x Gain)
GND
Figure 45. DAC8551 Architecture
The input coding to the DAC8551 is straight binary,
so the ideal output voltage is given by:
V _OUT
+
D_IN
65536
V _REF
(1)
where D_IN = decimal equivalent of the binary code
that is loaded to the DAC register; it can range from
0 to 65535.
RESISTOR STRING
The resistor string section is shown in Figure 46. It is
simply a string of resistors, each of value R. The
code loaded into the DAC register determines at
which node on the string the voltage is tapped off to
be fed into the output amplifier by closing one of the
switches connecting the string to the amplifier.
Monotonicity is ensured because of the string
resistor architecture.
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating
rail-to-rail voltages on its output, giving an output
range of 0V to V_DD. It is capable of driving a load of
2kΩ in parallel with 1000pF to GND. The source and
sink capabilities of the output amplifier can be seen
in the Typical Characteristics. The slew rate is
1.8V/µs with a full-scale setting time of 8µs with the
output unloaded.
The inverting input of the output amplifier is brought
out to the V_FB pin. This configuration allows for better
accuracy in critical applications by tying the V_FB point
and the amplifier output together directly at the load.
Other signal conditioning circuitry may also be
connected between these points for specific
applications.
R
R
Figure 46. Resistor String
SERIAL INTERFACE
The DAC8551 has a 3-wire serial interface (SYNC,
SCLK, and D_IN), which is compatible with SPI, QSPI,
and Microwire interface standards, as well as most
DSPs. See the Serial Write Operation Timing
Diagram for an example of a typical write sequence.
The write sequence begins by bringing the SYNC
line LOW. Data from the D_IN line are clocked into the
24-bit shift register on each falling edge of SCLK.
The serial clock frequency can be as high as 30MHz,
making the DAC8551 compatible with high-speed
DSPs. On the 24th falling edge of the serial clock,
the last data bit is clocked in and the programmed
function is executed (that is, a change in DAC
register contents and/or a change in the mode of
operation).
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