DAC8551IADGKRG4 Datasheet, PDF (18/26 Pages) Texas Instruments – 16-BIT, ULTRA-LOW GLITCH, VOLTAGE OUTPUT

DAC8551
SLAS429B – APRIL 2005 – REVISED OCTOBER 2006
MICROPROCESSOR INTERFACING
DAC8551 to 8051 Interface
See Figure 50 for a serial interface between the
DAC8551 and a typical 8051-type microcontroller.
The setup for the interface is as follows: TXD of the
8051 drives SCLK of the DAC8551, while RXD
drives the serial data line of the device. The SYNC
signal is derived from a bit-programmable pin on the
port of the 8051. In this case, port line P3.3 is used.
When data are to be transmitted to the DAC8551,
P3.3 is taken LOW. The 8051 transmits data in 8-bit
bytes; thus, only eight falling clock edges occur in
the transmit cycle. To load data to the DAC, P3.3 is
left LOW after the first eight bits are transmitted, then
a second write cycle is initiated to transmit the
second byte of data. P3.3 is taken HIGH following
the completion of the third write cycle. The 8051
outputs the serial data in a format that has the LSB
first. The DAC8551 requires data with the MSB as
the first bit received. The 8051 transmit routine must
therefore take this into account, and mirror the data
as needed.
80C51/80L51⁽¹⁾
P3.3
TXD
RXD
NOTE: (1) Additional pins omitted for clarity.
DAC8554⁽¹⁾
SYNC
SCLK
D_IN
Figure 50. DAC8551 to 80C51/80L51 Interface
DAC8551 to Microwire Interface
Figure 51 shows an interface between the DAC8551
and any Microwire-compatible device. Serial data are
shifted out on the falling edge of the serial clock and
is clocked into the DAC8551 on the rising edge of
the SK signal.
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Microwire^TM
CS
SK
SO
NOTE: (1) Additional pins omitted for clarity.
DAC8554⁽¹⁾
SYNC
SCLK
D_IN
Figure 51. DAC8551 to Microwire Interface
DAC8551 to 68HC11 Interface
Figure 52 shows a serial interface between the
DAC8551 and the 68HC11 microcontroller. SCK of
the 68HC11 drives the SCLK of the DAC8551, while
the MOSI output drives the serial data line of the
DAC. The SYNC signal is derived from a port line
(PC7), similar to the 8051 diagram.
68HC11⁽¹⁾
PC7
SCK
MOSI
NOTE: (1) Additional pins omitted for clarity.
DAC8551⁽¹⁾
SYNC
SCLK
D_IN
Figure 52. DAC8551 to 68HC11 Interface
The 68HC11 should be configured so that its CPOL
bit is '0' and its CPHA bit is '1'. This configuration
causes data appearing on the MOSI output to be
valid on the falling edge of SCK. When data are
being transmitted to the DAC, the SYNC line is held
LOW (PC7). Serial data from the 68HC11 are
transmitted in 8-bit bytes with only eight falling clock
edges occurring in the transmit cycle. (Data are
transmitted MSB first.) In order to load data to the
DAC8551, PC7 is left LOW after the first eight bits
are transferred, then a second and third serial write
operation are performed to the DAC. PC7 is taken
HIGH at the end of this procedure.
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