BQ24187 Datasheet, PDF (4/44 Pages) Texas Instruments – 1A USB-OTG Support

bq24187
SLUSBM0 – APRIL 2014
Not Recommended for New Designs
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TERMINAL
NAME
YFF RGE
DRV
D6
3
IN
C1-C4 18, 19
INT
E2
10
N.C.
PGND
PMID
D3, F2
A1-A6
B1
11, 15
21, 22
1
PSEL D4
14
SCL
D2
16
SDA
D1
17
STAT E1
13
SW
B2-B6 23, 24
CS+
E3-E6
6, 7
TS
D5
5
Thermal
PAD
–
–
Terminal Functions (continued)
I/O
DESCRIPTION
Gate Drive Supply. DRV is the bias supply for the gate drive of the internal MOSFETs. Bypass DRV
O to PGND with a 1μF ceramic capacitor. DRV may be used to drive external loads up to 10mA. DRV is
active whenever the input is connected and V_IN > V_UVLO and V_IN > (V_BAT + V_SLP).
I
DC Input Power Supply. IN is connected to the external DC supply (AC adapter or USB port). Bypass
IN to PGND with at least a 4.7μF ceramic capacitor.
Status Output. INT is an open-drain output that signals charging status and fault interrupts. INT pulls
low during charging. INT is high impedance when charging is complete or the charger is disabled.
O When a fault occurs, a 128μs pulse is sent out as an interrupt for the host. INT is enabled /disabled
using the EN_STAT bit in the control register. Connect INT to a logic rail through a 100kΩ resistor to
communicate with the host processor.
-- Connect to the ground plane of the circuit.
-- Ground terminal. Connect to the the ground plane of the circuit.
I
High Side Bypass Connection. Connect a 1µF capacitor from PMID to PGND as close to the PMID
and PGND TERMINALs as possible.
I
Hardware Input Current Limit. In DEFAULT mode, PSEL selects the input current limit during
DEFAULT mode. Drive PSEL high to select USB100 mode, drive PSEL low to select 1.5A mode.
I I²C Interface Clock. Connect SCL to the logic rail through a 10kΩ resistor.
I/O I²C Interface Data. Connect SDA to the logic rail through a 10kΩ resistor.
Status Output. STAT is an open-drain output that signals charging status and fault interrupts. STAT
pulls low during charging. STAT is high impedance when charging is complete or the charger is
O disabled. When a fault occurs, a 128μs pulse is sent out as an interrupt for the host. STAT is enabled
/disabled using the EN_STAT bit in the control register. Connect STAT to a logic rail using an LED for
visual indication or through a 10kΩ resistor to communicate with the host processor.
O Inductor Connection. Connect to the switched side of the external inductor.
I
System Voltage Sense and Charger FET Connection. Connect CS+ to the inductor. Bypass CS+
locally with 20μF.
Battery Pack NTC Monitor. Connect TS to the center tap of a resistor divider from DRV to GND. The
I
NTC is connected from TS to GND. The TS function provides 4 thresholds for JEITA compatibility. TS
faults are reported by the I²C interface. Pull TS high to V_DRV to disable the TS function. See the NTC
Monitor section for more details on operation and selecting the resistor values.
There is an internal electrical connection between the exposed thermal pad and the PGND
–
TERMINAL of the device. The thermal pad must be connected to the same potential as the PGND
TERMINAL on the printed circuit board. Do not use the thermal pad as the primary ground input for
the device. PGND TERMINAL must be connected to ground at all times.
4
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