BQ24187 Datasheet, PDF (34/44 Pages) Texas Instruments – 1A USB-OTG Support

bq24187
SLUSBM0 – APRIL 2014
10 Layout
Not Recommended for New Designs
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10.1 Layout Guidelines
It is important to pay special attention to the PCB layout. Figure 25 provides a sample layout for the high current
paths of the bq24187YFF.
The following provides some guidelines:
• Place 4.7µF input capacitor as close to IN terminal and PGND terminal as possible to make high frequency
current loop area as small as possible.
• Place 1µF input capacitor as close to PMID terminal and PGND terminal as possible to make high frequency
current loop area as small as possible. Connect the GND of the PMID and IN caps as close as possible.
• The local bypass capacitor from CS+ to GND should be connected between the CS+ terminal and PGND of
the IC. The intent is to minimize the current path loop area from the SW terminal through the LC filter and
back to the PGND terminal.
• Place all decoupling capacitor close to their respective IC terminal and as close as to PGND (do not place
components such that routing interrupts power stage currents). All small control signals should be routed
away from the high current paths.
• The PCB should have a ground plane (return) connected directly to the return of all components through vias
(two vias per capacitor for power-stage capacitors, one via per capacitor for small-signal components). It is
also recommended to put vias inside the PGND pads for the IC, if possible. A star ground design approach is
typically used to keep circuit block currents isolated (high-power/low-power small-signal) which reduces noise-
coupling and ground-bounce issues. A single ground plane for this design gives good results. With this small
layout and a single ground plane, there is no ground-bounce issue, and having the components segregated
minimizes coupling between signals.
• The high-current charge paths into IN, BAT, CS+ and from the SW terminals must be sized appropriately for
the maximum charge current in order to avoid voltage drops in these traces. The PGND terminals should be
connected to the ground plane to return current through the internal low-side FET.
• For high-current applications, the balls for the power paths should be connected to as much copper in the
board as possible. This allows better thermal performance as the board pulls heat away from the IC.
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