BQ24187 Datasheet, PDF (22/44 Pages) Texas Instruments – 1A USB-OTG Support

bq24187
SLUSBM0 – APRIL 2014
Not Recommended for New Designs
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Device Functional Modes (continued)
8.4.1.1.12 Charge Status Outputs (STAT, INT)
The STAT/INT output is used to indicate operation conditions for bq24187. STAT/INT is pulled low during
charging when EN_STAT bit in the control register is set to “1”. When charge is complete or disabled, STAT/INT
is high impedance. When a fault occurs, a 128-µs pulse (interrupt) is sent out to notify the host. The status of
STAT/INT during different operation conditions is summarized in Table 1. STAT/INT drives an LED for visual
indication or can be connected to the logic rail for host communication. The EN_STAT bit in the control register is
used to enable/disable the charge status for STAT/INT. The interrupt pulses are unaffected by EN_STAT and will
always be shown.
Table 1. STAT Terminal Summary
CHARGE STATE
Charge in progress and EN_STAT=1
Other normal conditions
Charge mode faults: Timer fault, sleep mode, VIN over voltage, VIN < UVLO, thermal shutdown
STAT
Low
High-Impedance
128-μs pulse, then High Impedance
8.4.2 Boost Mode Operation
In HOST mode, when the operation mode bit (BOOST_EN) in the control register (bit 6 in register 0x00h) is set
to 1, bq24187 operates in boost mode and delivers 5V to IN to supply USB OTG devices connected to the USB
connector. Boost operation can start with VBAT between 3.45V to 4.5V, and will maintain boost output until
VBAT falls to 3.3V. IN supplies up to 1A to power these devices. It is not recommended to operate boost mode
when the battery voltage is less than 3.3V. Proper operation is not guaranteed.
8.4.2.1 PWM Controller In Boost Mode
Similar to charge mode operation, in boost mode the IC switches at 1.5MHz to regulate the voltage at IN to 5V.
The voltage control loop is internally compensated to provide enough phase margin for stable operation with the
full battery voltage range and up to 750mA.
In boost mode, the cycle-by-cycle current limit is set to 4A or 2A (depending on the I²C setting) to provide
protection against short circuit conditions. If the cycle-by-cycle current limit is active for 8 ms, an overload
condition is detected and the device exits boost mode, and signals an over-current fault. Additionally, discharge
current limit (I_LIM(DISCH) is active to protect the battery from overload. Synchronous operation and burst mode are
used to maximize efficiency over the full load range.
The bq24187 will not enter boost mode unless the IN voltage is less than the UVLO and the IC is in high
impedance mode. When the boost function is enabled, the bq24187 enters a linear mode to bring IN up to the
battery voltage. Once V_IN > (V_BAT – 1V), the bq24187 begins switching and regulates IN up to 5V. If V_IN does not
rise to within 1V of V_BAT within 8ms, an over-current event is detected and boost mode is exited and a boost
mode over-current event is announced, the BOOST bit is reset to ‘0’ and the STAT_x and FAULT_x bits in the
Status/ Control register are updated.
8.4.2.2 Burst Mode During Light Load
In boost mode, the IC operates using burst mode to improve light load efficiency and reduce power loss. During
boost mode, the PWM converter is turned off when the devices reaches minimum duty cycle and the output
voltage rises to V_{BURST_ENT} threshold. This corresponds to approximately a 75mA inductor current. The converter
then restarts when V_IN falls to V_{BURST_EXT}. See Figure 21 in the Application Curves for an example waveform.
8.4.2.3 Watchdog Timer In Boost Mode
During boost mode, the watchdog timer is active. The watchdog timer works the same as in charge mode. Write
a “1” to the TMR_RST reset bit in the control register. If the watchdog timer expires, the IC resets the BOOST bit
to 0, signals the fault pulse on the STAT and INT terminals and sets fault status bits in the status register.
8.4.2.4 STAT/ INT During Boost Mode
During boost mode, the STAT and INT outputs are high impedance. Under fault conditions, a 128µs pulse is sent
out to notify the host of the error condition.
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