BQ24187 Datasheet, PDF (23/44 Pages) Texas Instruments – 1A USB-OTG Support

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Not Recommended for New Designs
bq24187
SLUSBM0 – APRIL 2014
8.4.2.5 Protection In Boost Mode
8.4.2.5.1 Output Over-Voltage Protection
The bq24187 contains integrated over-voltage protection on the IN terminal. During boost mode, if an over-
voltage condition is detected (V_IN.V_BOOSTOVP), the IC turns off the PWM converter, resets EN_BOOST bit to 0,
sets fault status bits and sends out a fault pulse on STAT and INT. The converter does not restart when VIN
drops to the normal level until the EN_BOOST bit is reset to 1.
8.4.2.5.2 Output Over-Current Protection
The bq24187 contains over current protection to prevent the device and battery damage when IN is overloaded.
When an over-current condition occurs, the cycle-by-cycle current limit limits the current from the battery to the
load. If the overload condition lasts for 8 consecutive cycles, the overload fault is detected. When an overload
condition is detected, the bq24187 turns off the PWM converter, resets BOOST bit to 0, sets the fault status bits
and sends out the fault pulse on STAT and INT. The boost starts only after the fault is cleared and the
EN_BOOST bit is reset to 1 using the I²C.
8.4.2.5.3 Battery Overvoltage Protection
During boost mode, when the battery voltage is below the minimum battery voltage threshold, VBATUVLO, the
IC turns off the PWM converter, resets BOOST bit to 0, sets fault status bits and sends out a fault pulse on STAT
and INT. Once the battery voltage returns to the acceptable level, the boost starts after the BOOST bit is set to 1.
Proper operation below 3.3V down to the V_BATUVLO is not specified.
8.5 Programming
8.5.1 Serial Interface Description
The bq24187 uses an I²C compatible interface to program charge parameters. I²C™ is a 2-wire serial interface
developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of
a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines
are pulled high. All the I²C compatible devices connect to the I²C bus through open drain I/O terminals, SDA and
SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is
responsible for generating the SCL signal and device addresses. The master also generates specific conditions
that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus
under control of the master device.
The bq24187 device works as a slave and supports the following data transfer modes, as defined in the I²C
Bus™ Specification: standard mode (100 kbps) and fast mode (400 kbps). The interface adds flexibility to the
battery charge solution, enabling most functions to be programmed to new values depending on the
instantaneous application requirements. Register contents remain intact as long as battery voltage remains
above 2.5 V (typical). The I²C circuitry is powered from VBUS when a supply is connected. If the VBUS supply is
not connected, the I²C circuitry is powered from the battery through CSOUT. The battery voltage must stay
above 2.5V with no input connected in order to maintain proper operation.
The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the
F/S-mode in this document. The bq24187/1 device only supports 7-bit addressing. The device 7-bit address is
defined as ‘1101011’ (0x6Bh).
8.5.1.1 F/S Mode Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 12. All I²C-compatible devices should
recognize a start condition.
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