TLC320AD50C-I_15 Datasheet, PDF (39/57 Pages) Texas Instruments – SIGMA-DELTA ANALOG INTERFACE CIRCUITS WITH MASTER-SLAVE FUNCTION

4.4.2 Slave Mode Timing Requirements
td4
tsu2
th2
td(FL–FDL)
td(CH–FDL)
twH
twL
Delay time, SCLK↑ to FS↓
Setup time, DIN, before SCLK low
Hold time, DIN, after SCLK low
Delay time, FS low to FSD low, (see Figure 5–2)
Delay time, SCLK high to FSD low, slave mode (see Figure 5–3)
Pulse duration, MCLK high
Pulse duration, MCLK low
MIN NOM MAX UNIT
0
20
20
40 _ns
50
32
20
4.4.3 Master Mode Switching Characteristics
td2
ten1
tdis1
PARAMETER
Delay time, SCLK↑ to DOUT
Enable time, FS↓ to DOUT
Disable time, FS↑ to DOUT Hi-Z
4.4.4 Slave Mode Switching Characteristics
td5
ten2
tdis2
PARAMETER
Delay time, SCLK↑ to DOUT
Enable time, FS↓ to DOUT
Disable time, FS↑ to DOUT Hi-Z
4.4.5 Reset Timing
tPW Reset pulsewidth
PARAMETER
TEST CONDITIONS
CL = 20 pF
MIN TYP MAX UNIT
20
25 ns
20
TEST CONDITIONS
CL = 20 pF
MIN TYP MAX UNIT
20
25 ns
20
MIN
6 MCLKs
TYP MAX UNIT
ns
4.4.6 Other
tsu3 Setup time, FC before FS↑
th3 Hold time, FC after FS↑
PARAMETER
MIN TYP MAX UNIT
10
ns
10
ns
4–6