TLC320AD50C-I_15 Datasheet, PDF (23/57 Pages) Texas Instruments – SIGMA-DELTA ANALOG INTERFACE CIRCUITS WITH MASTER-SLAVE FUNCTION

2.7.1 Frame Sync (FS) Function, Master Mode
The frame sync is generated internally and goes low on the rising edge of SCLK and remains low during a 16-bit data
transfer. In addition to generating its own frame-sync signal, the master also outputs a frame sync for each slave that
is being used (see Figures 2–8 and 2–9).
SCLK
FS
(see Note A)
FS
(see Note B)
Primary
16 SCLKs
Primary
Secondary
16 SCLKs
Primary
Primary
DIN/DOUT
128 SCLKs
256 SCLKs
NOTES: A. Primary and secondary serial communication
B. Primary serial communication, only
Figure 2–8. Master Device Frame-Sync Signal With Primary and Secondary Communications
(No Slaves)
SCLK
FS
(see Note A)
MP
SP
MS
SS
MP
FS
MP
SP
MP
(see Note B)
Delay is m Shift Clocks
(see Note C)
128 SCLKs
256 SCLKs
Legend:
MP:Master Primary (master device data is transferred in this period, DOUT of the slave device is in high impedance state).
SP: Slave Primary (slave device data is transferred in this period, DOUT of master device is in high impedance state).
MS:Master Secondary (master device control register information is transferred in this period, DOUT of the slave device is in high impedance state).
SS: Slave Secondary(slave device control register information is transferred in this period, DOUT of the master device is in high impedance state).
NOTES: A. Primary and secondary serial communications
B. Primary serial communication only
C. m is the value programmed into the FSD register (control register 3: D0 –D5)
Figure 2–9. Master Device Frame-Sync Signal With Primary and Secondary Communications
(With 1 Slave Device)
2.7.2 Frame Sync (FS) Function,Slave Mode
Frame-sync timing is generated externally by the master FSD (or the previous slave in a multislave configuration)
and is applied to FS of the slave to control the ADC and DAC timing.
2–8