TLC320AD50C-I_15 Datasheet, PDF (17/57 Pages) Texas Instruments – SIGMA-DELTA ANALOG INTERFACE CIRCUITS WITH MASTER-SLAVE FUNCTION

SCLK
FS
DOUT
(16-Bit)
DOUT
(15+1-Bit)
1
2
15
16
17
16 SCLKs
D15
D14
MSB
D15
D14
MSB
D1
D1
LSB
D0
LSB
M/S
NOTES: A. The 16-bit or (15 + 1)-bit mode is programmed via control register 2.
B. M/S is used to indicate whether the 15-bit data comes from master device or slave device. (Master: M/S = 1, Slave M/S = 0)
C. The MSB (D15) is stable (the host can latch the data in at this time) at the falling edge of SCLK #1, the last bit (D0,M/S) is stable
at the falling edge of SCLK #16.
Figure 2–1. Timing Sequence of ADC Channel (Primary Communication Only)
Primary
16 SCLKs
Secondary
16 SCLKs
Primary
FS
DOUT
(16-Bit)
DOUT
(15 +1-Bit)
16-Bit ADC Data
M/S + Register Address +
Register Data/
M/S + Register Address +
All 0s (see Note A)
15-Bit ADC Data
+ M/S
128 SCLKs
M/S + Register Data/
M/S + All 0 (see Note A)
256 SCLKs
NOTE A: M/S bit (DS15) in the secondary communication is used to indicate whether the register data (address and content) comes from the
master device or the slave device if the read bit is set. During register read operations, bits DS7 – DS0 are the contents of the specified
register. In register write operations, bits DS7 – DS0 are all 0s.
Figure 2–2. Timing Sequence of ADC Channel (Primary and Secondary Communication)
2.1.3 DAC Signal Channel
DIN receives the 16-bit serial data word (2s complement) from the host during the primary communications interval.
These 16-bit digital words, representing the analog output signal before PGA, are clocked into the serial port (DIN)
at the falling edge of SCLK during the frame-sync interval, one bit for each SCLK and one word for each primary
communication interval (256 SCLKs). The data are converted to a pulse train by the sigma-delta DAC, which consists
of a digital interpolation filter and a digital modulator. The output of the modulator is then passed to an internal
low-pass filter to complete the analog signal reconstruction. Finally, the resulting analog signal is applied to the input
of a programmable-gain amplifier, which is capable of driving a 600-Ω load differentially at OUTP and OUTM. The
timing sequence is shown in Figure 2–3.
2–2