TLC320AD50C-I_15 Datasheet, PDF (31/57 Pages) Texas Instruments – SIGMA-DELTA ANALOG INTERFACE CIRCUITS WITH MASTER-SLAVE FUNCTION

3.3 Conversion Rate Versus Serial Port
The SCLK frequency is set equal to the frequency of the frame-sync signal (FS) multiplied by 256. The conversion
rate or sample rate is equal to the frequency of FS.
3.4 Phone Mode Control
Phone mode control is provided for applications that need hardware control and monitoring of external events. By
allowing the device to drive the FLAG terminal (set through control 2 register), the host DSP is capable of system
control through the same serial port that connects the device. Along with this control is the capability of monitoring
the value of the ALTDATA terminal during a secondary communication cycle. One application for this function is in
monitoring RING DETECT or OFFHOOK DETECT from a phone answering system. FLAG allows response to these
incoming control signals. Figure 3–6 shows the timing associated with this operating mode.
P
S
FS
DOUT
(see Note A)
8-Bits
Register Data
(8-Bits)
DOUT
(see Note B)
16-Bits
ALTDATA
NOTES: A. When DIN performs a read operation (set D13 to 1) during secondary communication.
B. When DIN perform a write operation (set D13 to 0) during secondary communication.
Figure 3–6. Phone Mode Timing When Phone Mode Is Enabled
3.5 DIN and DOUT Data Format
3.5.1 Primary Serial Communication DIN and DOUT Data Format (Figure 3–7)
DIN
(15+1) Bit Mode
DOUT
(15+1) Bit Mode
D15 – D1
A/D and D/A Data
D15 – D1
D0
Secondary
Communication Request
D0
DIN
16-Bit Mode
D15 – D0
M/S Bit
A/D and D/A Data
DOUT
16-Bit Mode
D15 – D0
Figure 3–7. Primary Communication DIN and DOUT Data Format
3–4