TLC320AD50C-I_15 Datasheet, PDF (11/57 Pages) Texas Instruments – SIGMA-DELTA ANALOG INTERFACE CIRCUITS WITH MASTER-SLAVE FUNCTION

1.4 Ordering Information
TA
0°C to 70°C
–40°C to 85°C
PACKAGE
SMALL OUTLINE
PLASTIC DIP
(DW)
QUAD FLAT PACK
(PT)
TLC320AD50CDW
TLC320AD52CDW
TLC320AD50CPT
TLC320AD52CPT
TLC320AD50IDW
1.5 Terminal Functions
TERMINAL
NAME
NO. NO. ^I/O
PT DW
DESCRIPTION
ALTDATA
17 14
I Alternate data. ALTDATA signals are routed to DOUT during secondary communication if the phone mode
is enabled using control 2 register.
AUXM
48 4
AUXP
47 3
AVDD
37 25
AVDD(PLL) 5 7
AVSS
39 26
AVSS(PLL) 7 8
DIN
15 12
I Inverting input to auxiliary analog input. AUXM requires an external single-pole antialias filter with a low output
impedance and should be tied to AVSS if not used.
I Noninverting input to auxiliary analog input. AUXP requires an external single-pole antialias filter with a low
output impedance and should be tied to AVSS if not used.
I Analog ADC power supply (5 V only) (see Note 1)
I Analog power supply for the internal PLL (5 V only) (see Note 1)
I Analog ground (see Note 1)
I Analog ground for the internal PLL (see Note 1)
I Data input. DIN receives the DAC input data and register data from the external DSP (digital signal processor)
and is synchronized to SCLK and FS. Data is latched at the falling edge of SCLK when FS is low. DIN is at
high impedance when FS is not active.
DOUT
14 11 O Data output. DOUT transmits the ADC output bits and register data, and is synchronized to SCLK. Data is
sent out at the rising edge of SCLK when FS is low. DOUT is at high impedance when FS is not activated.
When configured as a master, DOUT is active only during the appropriate time slot. DOUT is in high
impedance during the frame syncs for the slaves.
DVDD
DVSS
FC
11 9
12 10
23 17
I Digital power supply (5 V or 3 V) (see Note 1)
I Digital ground (see Note 1)
I Hardware secondary communication request. When FC is set to high, a secondary communication, followed
by the primary communication, will occur to transfer data between this device and the external controller. FC
is sampled and latched on the rising edge of FS at the end of the primary serial communication. See section
3 for details.
FILT
43 28 O Bandgap filter. FILT is provided for decoupling of the bandgap reference, and provides 3.2 V. The optimal
capacitor value is 0.1 µF (ceramic). This voltage node should be loaded only with a high-impedance dc load.
FLAG
16 13 O Output flag. During phone mode, FLAG contains the value set in control 2 register.
FS
27 20 I/O Frame sync. FS is an output when the device is configured as a master (M/S pin tied high). FS is an input when
the device is configured as a slave (M/S pin tied low). When configured as a slave, data will transfer when
FS goes low. FS is internally generated in the master mode for the master device and all slave devices. In
the master mode FS is low during data transfer.
FSD
28 21 O Frame sync delayed output. The FSD (active-low) output synchronizes a slave device to the frame sync of
the master device. FSD is applied to the slave FS input and is the same duration as the master FS signal but
is delayed in time by the number of shift clocks programmed in the control 3 register.
INM
2 6 I Inverting input to analog modulator. INM requires an external single-pole antialias filter with a low output
impedance.
INP
1 5 I Noninverting input to analog modulator. INP requires an external single-pole antialias filter with a low output
impedance.
NOTES: 1. Separate analog and digital power and ground pins are supplied on this device. For best operation and results, the PC board designer
should utilize separate analog and digital power supplies as well as separate analog and digital ground planes.
2. All digital inputs and outputs are TTL compatible, unless otherwise noted (for DVDD = 5 V).
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