TCA8418E_15 Datasheet, PDF (34/50 Pages) Texas Instruments – I2C Controlled Keypad Scan IC With Integrated ESD Protection

TCA8418E
SCPS222C – MAY 2010 – REVISED OCTOBER 2015
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8.6.2.14 GPIO Edge/Level Detect Registers, GPIO_INT_LVL1–3 (Address 0x26–0x28)
A bit value of '0' indicates that interrupt will be triggered on a high-to-low/low-level transition for the inputs in
GPIO mode. This is the default value.
A bit value of 1 indicates that interrupt will be triggered on a low-to-high/high-level value for the inputs in GPIO
mode.
ADDRESS
0x26
0x27
0x28
Table 23. GPIO Edge/Level Detect Register Field Descriptions
REGISTER NAME
GPIO_INT_LVL1
GPIO_INT_LVL2
GPIO_INT_LVL3
REGISTER DESCRIPTION
GPIO Edge/Level Detect 1
GPIO Edge/Level Detect 2
GPIO Edge/Level Detect 3
7
R7IL
C7IL
N/A
6
R6IL
C6IL
N/A
5
R5IL
C5IL
N/A
BIT
4
3
R4IL R3IL
C4IL C3IL
N/A N/A
2
R2IL
C2IL
N/A
1
R1IL
C1IL
C9IL
0
R0IL
C0IL
C8IL
8.6.2.15 Debounce Disable Registers, DEBOUNCE_DIS1–3 (Address 0x29–0x2B)
This is for pins configured as inputs. A bit value of ‘0’ in any of the unreserved bits enables the debounce. This is
the default value
A bit value of ‘1’ disables the debounce.
ADDRESS
0x29
0x30
0x2B
Table 24. Debounce Disable Register Field Descriptions
REGISTER NAME
DEBOUNCE_DIS1
DEBOUNCE_DIS2
DEBOUNCE_DIS3
REGISTER DESCRIPTION
Debounce Disable 1
Debounce Disable 2
Debounce Disable 3
7
R7DD
C7DD
N/A
6
R6DD
C6DD
N/A
5
R5DD
C5DD
N/A
BIT
4
3
R4DD R3DD
C4DD C3DD
N/A N/A
2
R2DD
C2DD
N/A
1
R1DD
C1DD
C9DD
0
R0DD
C0DD
C8DD
DEBOUNCE ENABLED
GPI with INT
INT
50 ms
VALID HIGH TRIGGER INTERRUPT
50 ms
VALID LOW TRIGGER INTERRUPT
DEBOUNCE DISABLED
GPI with INT
INT
VALID HIGH TRIGGER INTERRUPT
VALID LOW TRIGGER INTERRUPT
Figure 27. Debounce Enabled and Disabled
Debounce disable will have the same effect for GPI mode or for rows in keypad scanning mode. The RESET
input always has a 50-μs debounce time.
The debounce time for inputs is the time required for the input to be stable to be noticed. This time is 50 μs.
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