TCA8418E_15 Datasheet, PDF (29/50 Pages) Texas Instruments – I2C Controlled Keypad Scan IC With Integrated ESD Protection

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TCA8418E
SCPS222C – MAY 2010 – REVISED OCTOBER 2015
8.6.2.1 Configuration Register (Address 0x01)
Table 10. Configuration Register Field Descriptions
BIT
NAME
DESCRIPTION
Auto-increment for read and write operations; See below table for more information
7
AI
0 = disabled
1 = enabled
GPI event mode configuration
6
GPI_E_CFG
0 = GPI events are tracked when keypad is locked
1 = GPI events are not tracked when keypad is locked
Overflow mode
5
OVR_FLOW_M
0 = disabled; Overflow data is lost
1 = enabled; Overflow data shifts with last event pushing first event out
Interrupt configuration
4
INT_CFG
0 = processor interrupt remains asserted (or low) if host tries to clear interrupt while there is
still a pending key press, key release or GPI interrupt
1 = processor interrupt is deasserted for 50 μs and reassert with pending interrupts
Overflow interrupt enable
3
OVR_FLOW_IEN
0 = disabled; INT is not asserted if the FIFO overflows
1 = enabled; INT becomes asserted if the FIFO overflows
Keypad lock interrupt enable
2
K_LCK_IEN
0 = disabled; INT is not asserted after a correct unlock key sequence
1 = enabled; INT becomes asserted after a correct unlock key sequence
GPI interrupt enable to host processor
1
GPI_IEN
0 = disabled; INT is not asserted for a change on a GPI
1 = enabled; INT becomes asserted for a change on a GPI
Key events interrupt enable to host processor
0
KE_IEN
0 = disabled; INT is not asserted when a key event occurs
1 = enabled; INT becomes asserted when a key event occurs
Bit 7 in this register is used to determine the programming mode. If it is low, all data bytes are written to the
register defined by the command byte. If bit 7 is high, the value of the command byte is automatically
incremented after each byte is written, and the next data byte is stored in the corresponding register. Registers
are written in the sequence shown in Table 9. Once the GPIO_PULL3 register (0x2E) is written to, the command
byte returns to register 0. Registers 0 and 2F are reserved and a command byte that references these registers
is not acknowledged by the TCA8418E.
The keypad lock interrupt enable determines if the interrupt pin is asserted when the key lock interrupt (see
Interrupt Status Register) bit is set.
8.6.2.2 Interrupt Status Register, INT_STAT (Address 0x02)
Table 11. Interrupt Status Register Field Descriptions
BIT
NAME
7
N/A
Always 0
6
N/A
Always 0
5
N/A
Always 0
DESCRIPTION
CTRL-ALT-DEL key sequence status. Requires writing a 1 to clear interrupts.
4
CAD_INT
0 = interrupt not detected
1 = interrupt detected
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