TCA8418E_15 Datasheet, PDF (30/50 Pages) Texas Instruments – I2C Controlled Keypad Scan IC With Integrated ESD Protection

TCA8418E
SCPS222C – MAY 2010 – REVISED OCTOBER 2015
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Table 11. Interrupt Status Register Field Descriptions (continued)
BIT
NAME
DESCRIPTION
Overflow interrupt status. Requires writing a 1 to clear interrupts.
3
OVR_FLOW_INT
0 = interrupt not detected
1 = interrupt detected
Keypad lock interrupt status. This is the interrupt to the processor when the keypad lock
sequence is started. Requires writing a 1 to clear interrupts.
2
K_LCK_INT
0 = interrupt not detected
1 = interrupt detected
GPI interrupt status. Requires writing a 1 to clear interrupts.
1
GPI_INT
0 = interrupt not detected
1 = interrupt detected
Can be used to mask interrupts
Key events interrupt status. Requires writing a 1 to clear interrupts.
0
K_INT
0 = interrupt not detected
1 = interrupt detected
The INT_STAT register is used to check which type of interrupt has been triggered. If the corresponding interrupt
enable bits are set in the Configuration Register, then a value of 1 in the corresponding bit will assert the INT line
low. An exception to this is the CAD_INT bit, which will assert the CAD_INT pin on YFP packages.
A read to this register will return which types of events have occurred. Writing a 1 to the bit will clear the
interrupt, unless there is still data which has set the Interrupt (unread keys in the FIFO).
8.6.2.3 Key Lock and Event Counter Register, KEY_LCK_EC (Address 0x03)
Table 12. Key Lock and Event Counter Register Field Descriptions
BIT
NAME
7
N/A
Always 0
DESCRIPTION
Key lock enable
6
K_LCK_EN
0 = disabled; Write a 0 to this bit to unlock the keypad manually
1 = enabled; Write a 1 to this bit to lock the keypad
Keypad lock status
5
LCK2
0 = unlock (if LCK1 is 0 too)
1 = locked (if LCK1 is 1 too)
Keypad lock status
4
LCK1
0 = unlock (if LCK2 is 0 too)
1 = locked (if LCK2 is 1 too)
3
KEC3
Key event count, Bit 3
2
KEC2
Key event count, Bit 2
1
KEC1
Key event count, Bit 1
0
KEC0
Key event count, Bit 0
30
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