TCA8418E_15 Datasheet, PDF (33/50 Pages) Texas Instruments – I2C Controlled Keypad Scan IC With Integrated ESD Protection

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TCA8418E
SCPS222C – MAY 2010 – REVISED OCTOBER 2015
A bit value of '0' in any of the unreserved bits disables the corresponding pin's ability to generate an interrupt
when the state of the input changes. This is the default value.
A bit value of 1 in any of the unreserved bits enables the corresponding pin's ability to generate an interrupt
when the state of the input changes.
ADDRESS
0x1A
0x1B
0x1C
Table 19. GPIO Interrupt Enable Register Field Descriptions
REGISTER NAME
GPIO_INT_EN1
GPIO_INT_EN2
GPIO_INT_EN3
REGISTER DESCRIPTION
GPIO Interrupt Enable 1
GPIO Interrupt Enable 2
GPIO Interrupt Enable 3
7
R7IE
C7IE
N/A
6
R6IE
C6IE
N/A
5
R5IE
C5IE
N/A
BIT
4
3
R4IE R3IE
C4IE C3IE
N/A N/A
2
R2IE
C2IE
N/A
1
R1IE
C1IE
C9IE
0
R0IE
C0IE
C8IE
8.6.2.11 Keypad or GPIO Selection Registers, KP_GPIO1–3 (Address 0x1D–0x1F)
A bit value of '0' in any of the unreserved bits puts the corresponding pin in GPIO mode. A pin in GPIO mode can
be configured as an input or an output in the GPIO_DIR1-3 registers. This is the default value.
A 1 in any of these bits puts the pin in key scan mode and becomes part of the keypad array, then it is
configured as a row or column accordingly (this is not adjustable).
ADDRESS
0x1D
0x1E
0x1F
Table 20. Keypad or GPIO Selection Register Field Descriptions
REGISTER NAME
KP_GPIO1
KP_GPIO2
KP_GPIO3
REGISTER DESCRIPTION
Keypad/GPIO Select 1
Keypad/GPIO Select 2
Keypad/GPIO Select 3
BIT
7
6
5
4
3
2
1
0
ROW7 ROW6 ROW5 ROW4 ROW3 ROW2 ROW1 ROW0
COL7 COL6 COL5 COL4 COL3 COL2 COL1 COL0
N/A N/A N/A N/A N/A N/A COL9 COL8
8.6.2.12 GPI Event Mode Registers, GPI_EM1–3 (Address 0x20–0x22)
A bit value of '0' in any of the unreserved bits indicates that it is not part of the event FIFO. This is the default
value.
A 1 in any of these bits means it is part of the event FIFO. When a pin is setup as a GPI and has a value of 1 in
the Event Mode register, then any key presses will be added to the FIFO. Please see Key Event Table for more
information.
ADDRESS
0x20
0x21
0x23
Table 21. GPI Event Mode Register Field Descriptions
REGISTER NAME
GPI_EM1
GPI_EM2
GPI_EM3
REGISTER DESCRIPTION
GPI Event Mode Select 1
GPI Event Mode Select 2
GPI Event Mode Select 3
BIT
7
6
5
4
3
2
1
0
ROW7 ROW6 ROW5 ROW4 ROW3 ROW2 ROW1 ROW0
COL7 COL6 COL5 COL4 COL3 COL2 COL1 COL0
N/A N/A N/A N/A N/A N/A COL9 COL8
8.6.2.13 GPIO Data Direction Registers, GPIO_DIR1–3 (Address 0x23–0x25)
A bit value of '0' in any of the unreserved bits sets the corresponding pin as an input. This is the default value.
A 1 in any of these bits sets the pin as an output.
ADDRESS
0x23
0x24
0x25
Table 22. GPIO Data Direction Register Field Descriptions
REGISTER NAME
GPIO_DIR1
GPIO_DIR2
GPIO_DIR3
REGISTER DESCRIPTION
GPIO Direction 1
GPIO Direction 2
GPIO Direction 3
7
R7DD
C7DD
N/A
6
R6DD
C6DD
N/A
5
R5DD
C5DD
N/A
BIT
4
3
R4DD R3DD
C4DD C3DD
N/A N/A
2
R2DD
C2DD
N/A
1
R1DD
C1DD
C9DD
0
R0DD
C0DD
C8DD
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