DS90UB925Q Datasheet, PDF (34/41 Pages) Texas Instruments – 5 - 85 MHz 24-bit Color FPD-Link III Serializer with Bidirectional Control Channel

DS90UB925Q
ADD
(dec)
101
102
103
198
ADD
(hex)
0x65
Register
Name
Pattern
Generator
Configuration
0x66
Pattern
Generator
Indirect
Address
0x67 Pattern
Generator
Indirect Data
0xC6 ICR
Bit(s)
Register
Type
7:5
4
RW
3
RW
2
RW
1
RW
0
RW
7:0 RW
7:0 RW
7:6
5
RW
4:1
0
RW
Default
(hex)
0x00
0x00
0x00
Function Description
Reserved
Pattern
Generator
18 Bits
18-bit Mode Select
1: Enable 18-bit color pattern generation. Scaled
patterns will have 64 levels of brightness and the R,
G, and B outputs use the six most significant color
bits.
0: Enable 24-bit pattern generation. Scaled patterns
use 256 levels of brightness.
Pattern
Generator
External
Clock
Select External Clock Source
1: Selects the external pixel clock when using
internal timing.
0: Selects the internal divided clock when using
internal timing
This bit has no effect in external timing mode
(PATGEN_TSEL = 0).
Pattern
Generator
Timing
Select
Timing Select Control
1: The Pattern Generator creates its own video
timing as configured in the Pattern Generator Total
Frame Size, Active Frame Size. Horizontal Sync
Width, Vertical Sync Width, Horizontal Back Porch,
Vertical Back Porch, and Sync Configuration
registers.
0: the Pattern Generator uses external video timing
from the pixel clock, Data Enable, Horizontal Sync,
and Vertical Sync signals.
Pattern Enable Inverted Color Patterns
Generator 1: Invert the color output.
Color Invert 0: Do not invert the color output.
Pattern Auto-Scroll Enable:
Generator 1: The Pattern Generator will automatically move to
Auto-Scroll the next enabled pattern after the number of frames
Enable
specified in the Pattern Generator Frame Time
(PGFT) register.
0: The Pattern Generator retains the current pattern.
Indirect
Address
This 8-bit field sets the indirect address for accesses
to indirectly-mapped registers. It should be written
prior to reading or writing the Pattern Generator
Indirect Data register.
See AN-2198
Indirect
Data
When writing to indirect registers, this register
contains the data to be written. When reading from
indirect registers, this register contains the read
back value.
See AN-2198
Reserved
IS_RX_INT Interrupt on Receiver interrupt
Enables interrupt on indication from the Receiver.
Allows propagation of interrupts from downstream
devices
Reserved
INT Enable Global Interrupt Enable
Enables interrupt on the interrupt signal to the
controller.
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