DS90UB925Q Datasheet, PDF (32/41 Pages) Texas Instruments – 5 - 85 MHz 24-bit Color FPD-Link III Serializer with Bidirectional Control Channel

DS90UB925Q
ADD
(dec)
24
25
27
ADD
(hex)
0x18
0x19
0x1B
Register
Name
Bit(s)
Register
Type
SCL High Time 7:0 RW
SCL Low Time 7:0 RW
BIST BC Error 7:0
R
Default
(hex)
0xA1
0xA5
0x00
Function
SCL HIGH
Time
SCL LOW
Time
BIST Back
Channel
CRC Error
Counter
Description
I2C Master SCL High Time
This field configures the high pulse width of the SCL
output when the Serializer is the Master on the local
I2C bus. Units are 40 ns for the nominal oscillator
clock frequency. The default value is set to provide
a minimum 5us SCL high time with the internal
oscillator clock running at 32.5MHz rather than the
nominal 25MHz.
I2C SCL Low Time
This field configures the low pulse width of the SCL
output when the Serializer is the Master on the local
I2C bus. This value is also used as the SDA setup
time by the I2C Slave for providing data prior to
releasing SCL during accesses over the
Bidirectional Control Channel. Units are 40 ns for
the nominal oscillator clock frequency. The default
value is set to provide a minimum 5us SCL low time
with the internal oscillator clock running at 32.5MHz
rather than the nominal 25MHz.
BIST Mode Back Channel CRC Error Counter
This error counter is active only in the BIST mode.
It clears itself at the start of the BIST run.
32
Copyright © 1999-2012, Texas Instruments Incorporated