DS90UB925Q Datasheet, PDF (22/41 Pages) Texas Instruments – 5 - 85 MHz 24-bit Color FPD-Link III Serializer with Bidirectional Control Channel

DS90UB925Q
Forward Channel and Back Channel Error Checking
While in BIST mode, the serializer stops sampling RGB input pins and switches over to an internal all-zero pattern. The internal
all-zeroes pattern goes through scrambler, dc-balancing etc. and goes over the serial link to the deserializer. The deserializer on
locking to the serial stream compares the recovered serial stream with all-zeroes and records any errors in status registers and
dynamically indicates the status on PASS pin. The deserializer then outputs a SSO pattern on the RGB output pins.
The back-channel data is checked for CRC errors once the serializer locks onto back-channel serial stream as indicated by link
detect status (register bit 0x0C[0]). The CRC errors are recorded in an 8-bit register. The register is cleared when the serializer
enters the BIST mode. As soon as the serializer exits BIST mode, the functional mode CRC register starts recording the CRC
errors. The BIST mode CRC error register is active in BIST mode only and keeps the record of last BIST run until cleared or enters
BIST mode again.
FIGURE 16. BIST Waveforms
30143364
Internal Pattern Generation
The DS90UB925Q serializer supports the internal pattern generation feature. It allows basic testing and debugging of an integrated
panel through the FPD-Link III output stream. The test patterns are simple and repetitive and allow for a quick visual verification of
panel operation. As long as the device is not in power down mode, the test pattern will be displayed even if no parallel input is
applied. If no PCLK is received, the test pattern can be configured to use a programmed oscillator frequency. For detailed infor-
mation, refer to Application Note AN-2198.
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