DS90UB925Q Datasheet, PDF (14/41 Pages) Texas Instruments – 5 - 85 MHz 24-bit Color FPD-Link III Serializer with Bidirectional Control Channel

DS90UB925Q
Functional Description
The DS90UB925Q serializer transmits a 35-bit symbol over a single serial FPD-Link III pair operating up to 2.975 Gbps line rate.
The serial stream contains an embedded clock, video control signals and DC-balanced video data and audio data which enhance
signal quality to support AC coupling. The serializer is intended for use with the DS90UB926Q deserializer, but is also backward
compatible with DS90UR906Q or DS90UR908Q FPD-Link II deserializer.
The DS90UB925Q serializer and DS90UB926Q deserializer incorporate an I2C compatible interface. The I2C compatible interface
allows programming of serializer or deserializer devices from a local host controller. In addition, the devices incorporate a bidirec-
tional control channel (BCC) that allows communication between serializer/deserializer as well as remote I2C slave devices.
The bidirectional control channel is implemented via embedded signaling in the high-speed forward channel (serializer to deseri-
alizer) as well as lower speed signaling in the reverse channel (deserializer to serializer). Through this interface, the BCC provides
a mechanism to bridge I2C transactions across the serial link from one I2C bus to another. The implementation allows for arbitration
with other I2C compatible masters at either side of the serial link.
There are two operating modes available on DS90UB925Q, display mode and camera mode. In display mode, I2C transactions
originate from the host controller attached to the serializer and target either the deserializer or an I2C slave attached to the dese-
rializer. Transactions are detected by the I2C slave in the serializer and forwarded to the I2C master in the deserializer. Similarly,
in camera mode, I2C transactions originate from a controller attached to the deserializer and target either the serializer or an I2C
slave attached to the serializer. Transactions are detected by the I2C slave in the deserializer and forwarded to the I2C master in
the serializer.
HIGH SPEED FORWARD CHANNEL DATA TRANSFER
The High Speed Forward Channel (HS_FC) is composed of 35 bits of data containing DIN[23:0] or RGB[7:0] or YUV data, sync
signals, I2C, and I2S audio transmitted from Serializer to Deserializer. Figure 9 illustrates the serial stream per PCLK cycle. This
data payload is optimized for signal transmission over an AC coupled link. Data is randomized, balanced and scrambled.
FIGURE 9. FPD-Link III Serial Stream
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The device supports clocks in the range of 5 MHz to 85 MHz. The application payload rate is 2.975 Gbps maximum (175 Mbps
minimum) with the actual line rate of 2.975 Gbps maximum and 525 Mbps Minimum.
LOW SPEED BACK CHANNEL DATA TRANSFER
The Low-Speed Backward Channel (LS_BC) of the DS90UB925Q provides bidirectional communication between the display and
host processor. The information is carried back from the Deserializer to the Serializer per serial symbol. The back channel control
data is transferred over the single serial link along with the high-speed forward data, DC balance coding and embedded clock
information. This architecture provides a backward path across the serial link together with a high speed forward channel. The back
channel contains the I2C, CRC and 4 bits of standard GPIO information with 10 Mbps line rate.
BACKWARD COMPATIBLE MODE
The DS90UB925Q is also backward compatible to DS90UR906Q and DS90UR908Q FPD Link II deserializers at 5-65 MHz of
PCLK. It transmits 28-bits of data over a single serial FPD-Link II pair operating at the line rate of 140 Mbps to 1.82 Gbps. The
backward configuration mode can be set via MODE_SEL pin (Table 1) or the configuration register (Table 6).
COMMON MODE FILTER PIN (CMF)
The serializer provides access to the center tap of the internal termination. A capacitor must be placed on this pin for additional
common-mode filtering of the differential pair. This can be useful in high noise environments for additional noise rejection capability.
A 0.1 μF capacitor must be connected to this pin to Ground.
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