DS90UB925Q Datasheet, PDF (26/41 Pages) Texas Instruments – 5 - 85 MHz 24-bit Color FPD-Link III Serializer with Bidirectional Control Channel

DS90UB925Q
ADD
(dec)
4
5
ADD
(hex)
0x04
Register
Name
Configuration
1
0x05 I2C Control
Bit(s)
Register
Type
7
RW
6
5
RW
4
3
RW
2
RW
1
RW
0
RW
7:5
4:3 RW
2
RW
1
RW
0
RW
Default
(hex)
0x80
0x00
Function Description
Failsafe
State
Input Failsafe State
1: Failsafe to Low
0: Failsafe to High
Reserved
CRC Error
Reset
Clear back channel CRC Error Counters
This bit is NOT self-clearing
1: Clear Counters
0: Normal Operation
Reserved
BKWD
Override
Backward Compatible mode set by MODE_SEL pin
or register
1: BC to DS90UR906Q or DS90UR908Q mode is
set by register bit
0: BC to DS90UR906Q or DS90UR908Q mode is
set by MODE_SEL pin. .
BKWD
Backward compatibility mode, device to pair with
DS90UR906Q or DS90UR908Q
1: Compatible with DS90UR906Q or DS90UR908Q
0: Normal device
LFMODE
Override
Frequency mode set by MODE_SEL pin or register
1: Frequency mode is set by register bit
0: Frequency mode is set by MODE_SEL Pin
LFMODE
Frequency mode select
1:Low frequency mode (5MHz - <15 MHz)
0: High frequency mode (15MHz - 85MHz)
Reserved
SDA
Output
Delay
SDA output delay
Configures output delay on the SDA output. Setting
this value will increase output delay in units of 40ns.
Nominal output delay values for SCL to SDA are
00: 240ns
01: 280ns
10: 320ns
11: 360ns
Local Write Disable remote writes to local registers
Disable Setting the bit to a 1 prevents remote writes to local
device registers from across the control channel. It
prevents writes to the Serializer registers from an
I2C master attached to the Deserializer.
Setting this bit does not affect remote access to I2C
slaves at the Serializer
I2C Bus
Timer
Speedup
Speed up I2C bus watchdog timer
1: Watchdog timer expires after ~50 ms.
0: Watchdog Timer expires after ~1 s
I2C Bus
timer
Disable
Disable I2C bus watchdog timer
When the I2C watchdog timer may be used to detect
when the I2C bus is free or hung up following an
invalid termination of a transaction.
If SDA is high and no signalling occurs for ~1 s, the
I2C bus assumes to be free. If SDA is low and no
signaling occurs, the device attempts to clear the
bus by driving 9 clocks on SCL
26
Copyright © 1999-2012, Texas Instruments Incorporated