DS90UB925Q Datasheet, PDF (24/41 Pages) Texas Instruments – 5 - 85 MHz 24-bit Color FPD-Link III Serializer with Bidirectional Control Channel

DS90UB925Q
The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when SCL transitions
Low while SDA is High. A STOP occurs when SDA transition High while SCL is also HIGH. See Figure 18.
FIGURE 18. START and STOP Conditions
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To communicate with a remote device, the host controller (master) sends the slave address and listens for a response from the
slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is addressed correctly, it Acknowledges
(ACKs) the master by driving the SDA bus low. If the address doesn't match a device's slave address, it Not-acknowledges (NACKs)
the master by letting SDA be pulled High. ACKs also occur on the bus when data is being transmitted. When the master is writing
data, the slave ACKs after every data byte is successfully received. When the master is reading data, the master ACKs after every
data byte is received to let the slave know it wants to receive another data byte. When the master wants to stop reading, it NACKs
after the last data byte and creates a stop condition on the bus. All communication on the bus begins with either a Start condition
or a Repeated Start condition. All communication on the bus ends with a Stop condition. A READ is shown in Figure 19 and a
WRITE is shown in Figure 20.
If the Serial Bus is not required, the three pins may be left open (NC).
FIGURE 19. Serial Control Bus — READ
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FIGURE 20. Serial Control Bus — WRITE
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