TLC320AD80 Datasheet, PDF (32/37 Pages) Texas Instruments – Audio Processor Subsystem

Appendix A
Register Set
Control of the TLC320AD80 is accomplished by means of the SPI serial interface and the control registers
described in this section.
There are five control registers used to control the various functions of the device: volume control,
multiplexer selections, serial interface, modes of operation, etc.
Table A–1. Serial PCM Data Format Control Register (Control Register 00h)
D7 D6 D5 D4 D3 D2 D1 D0
00––––––
FUNCTION
Philips I2S protocol
01–
–
–
–
– – _{Serial PCM}
Right justified
10–
–
–
–
– – ^{data format}
Left justified
11––––––
Left justified DSP (inverted BCLK)
––0
–
–
–
– – _{Serial PCM}
16 bits
– – 1 – – – – – ^{data precision} 18 bits
–––00–––
256 x LRCLK (22.05 kHz ≤ LRCLK ≤ 48 kHz)
– – – 0 1 – – – MCLK rate
384 x LRCLK (22.05 kHz ≤ LRCLK ≤ 48 kHz)
–––10–––
512 x LRCLK (8 kHz ≤ LRCLK ≤ 16 kHz)
– – – 1 1 – – – Reserved
–––––00–
64 x LRCLK
–
–
–
–
–
0
1
–
Bit clock
(BCLK) rate
48 x LRCLK (384x mode only)
–––––10–
32 x LRCLK (16-bit mode only)
– – – – – 1 1 – Reserved
– – – – – – – x Reserved
The default value at reset is 00h.
A–1